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coreboot-kgpe-d16
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Rampayload: Able to build coreboot without ramstage 

This patch removes all possible dependencies in order to build platform
with CONFIG_RAMPAYLOAD enable(without ramstage).

A. Create coreboot separate stage kconfigs

This patch creates seperate stage configs as below
1. HAVE_BOOTBLOCK
2. HAVE_VERSTAGE
3. HAVE_ROMSTAGE
4. HAVE_POSTCAR
5. HAVE_RAMSTAGE

B. Also ensures below kconfigs are aligned with correct stage configs

1. COMPRESS_RAMSTAGE and RELOCATABLE_RAMSTAGE are now enable if
CONFIG_HAVE_RAMSTAGE is selected.
2. COMPRESS_BOOTBLOCK will enable if CONFIG_HAVE_BOOTBLOCK is set
3. COMPRESS_PRERAM_STAGES will enable if CONFIG_HAVE_VERSTAGE
|| CONFIG_HAVE_ROMSTAGE is selected.

C. Also fix compilation issue with !CONFIG_HAVE_RAMSTAGE

On x86 platform:
Case 1: ramstage do exist: CONFIG_HAVE_RAMSTAGE=1
>> rmodules_$(ARCH-ramstage-y) will evaluate as rmodules_x86_32

Case 2: ramstage doesn't exist: CONFIG_HAVE_RAMSTAGE=0
>> rmodules_$(ARCH-ramstage-y) will evaluate as rmodules_

This patch fixes Case 2 usecase where platform doesn't select
CONFIG_HAVE_RAMSTAGE.

Also add option to create sipi_vector.manual based on $(TARGET_STAGE)
variable.

$(TARGET_STAGE)=ramstage if user selects CONFIG_HAVE_RAMSTAGE
$(TARGET_STAGE)=postcar if user selects CONFIG_RAMPAYLOAD

Change-Id: I0f7e4174619016c5a54c28bedd52699df417a5b7
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33142
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Subrata Banik 2019-06-08 12:29:02 +05:30
parent 2395917adf
commit b5962a934a
3 changed files with 55 additions and 18 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
Makefile.inc
View File

@ -1058,7 +1058,14 @@ ifneq ($(FIT_ENTRY),)
FIT_OPTIONS += -q $(FIT_ENTRY)
endif
$(obj)/coreboot.rom: $(obj)/coreboot.pre $(objcbfs)/ramstage.elf $(CBFSTOOL) $$(INTERMEDIATE)
ifeq ($(CONFIG_HAVE_RAMSTAGE),y)
RAMSTAGE=$(objcbfs)/ramstage.elf
else
RAMSTAGE=
endif
$(obj)/coreboot.rom: $(obj)/coreboot.pre $(RAMSTAGE) $(CBFSTOOL) $$(INTERMEDIATE)
@printf " CBFS $(subst $(obj)/,,$(@))\n"
# The full ROM may be larger than the CBFS part, so create an empty
# file (filled with \377 = 0xff) and copy the CBFS image over it.
@ -1128,8 +1135,8 @@ endif # CONFIG_NO_FIXED_XIP_ROM_SIZE
endif # CONFIG_NO_XIP_EARLY_STAGES
endif # CONFIG_ARCH_ROMSTAGE_X86_32 / CONFIG_ARCH_ROMSTAGE_X86_64
cbfs-files-y += $(CONFIG_CBFS_PREFIX)/ramstage
$(CONFIG_CBFS_PREFIX)/ramstage-file := $(objcbfs)/ramstage.elf
cbfs-files-$(CONFIG_HAVE_RAMSTAGE) += $(CONFIG_CBFS_PREFIX)/ramstage
$(CONFIG_CBFS_PREFIX)/ramstage-file := $(RAMSTAGE)
$(CONFIG_CBFS_PREFIX)/ramstage-type := stage
$(CONFIG_CBFS_PREFIX)/ramstage-compression := $(CBFS_COMPRESS_FLAG)

28
src/Kconfig
View File

@ -129,6 +129,7 @@ config STATIC_OPTION_TABLE
config COMPRESS_RAMSTAGE
bool "Compress ramstage with LZMA"
depends on HAVE_RAMSTAGE
# Default value set at the end of the file
help
Compress ramstage to save memory in the flash image. Note
@ -137,7 +138,7 @@ config COMPRESS_RAMSTAGE
config COMPRESS_PRERAM_STAGES
bool "Compress romstage and verstage with LZ4"
depends on !ARCH_X86
depends on !ARCH_X86 && (HAVE_ROMSTAGE || HAVE_VERSTAGE)
# Default value set at the end of the file
help
Compress romstage and (if it exists) verstage with LZ4 to save flash
@ -148,6 +149,7 @@ config COMPRESS_PRERAM_STAGES
config COMPRESS_BOOTBLOCK
bool
depends on HAVE_BOOTBLOCK
help
This option can be used to compress the bootblock with LZ4 and attach
a small self-decompression stub to its front. This can drastically
@ -234,6 +236,7 @@ config NO_RELOCATABLE_RAMSTAGE
config RELOCATABLE_RAMSTAGE
bool
depends on HAVE_RAMSTAGE
default !NO_RELOCATABLE_RAMSTAGE
select RELOCATABLE_MODULES
help
@ -1191,3 +1194,26 @@ config BOOTSPLASH_FILE
config CBFS_SIZE
default ROM_SIZE
config HAVE_BOOTBLOCK
bool
default y
config HAVE_VERSTAGE
bool
depends on VBOOT_SEPARATE_VERSTAGE
default y
config HAVE_ROMSTAGE
bool
default y
config HAVE_POSTCAR
bool
depends on POSTCAR_STAGE
default y
config HAVE_RAMSTAGE
bool
default n if RAMPAYLOAD
default y

32
src/cpu/x86/Makefile.inc
View File

@ -17,23 +17,27 @@ SIPI_RMOD=$(SIPI_ELF).rmod
SIPI_BIN=$(SIPI_ELF:.elf=)
SIPI_DOTO=$(SIPI_ELF:.elf=.o)
ifeq ($(CONFIG_PARALLEL_MP),y)
ramstage-srcs += $(SIPI_BIN).manual
endif
rmodules_$(ARCH-ramstage-y)-$(CONFIG_PARALLEL_MP) += sipi_vector.S
$(SIPI_DOTO): $(call src-to-obj,rmodules_$(ARCH-ramstage-y),src/cpu/x86/sipi_vector.S)
$(CC_rmodules_$(ARCH-ramstage-y)) $(CFLAGS_rmodules_$(ARCH-ramstage-y)) -nostdlib -r -o $@ $^
ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y)
$(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_DOTO), 0,x86_32))
ifeq ($(CONFIG_HAVE_RAMSTAGE),y)
TARGET_STAGE=ramstage
else ifeq ($(CONFIG_RAMPAYLOAD),y)
TARGET_STAGE=postcar
else
$(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_DOTO), 0,x86_64))
$(error Halting the build due to unknown TARGET_STAGE select)
endif
ifeq ($(CONFIG_PARALLEL_MP),y)
$(TARGET_STAGE)-srcs += $(SIPI_BIN).manual
endif
rmodules_$(ARCH-$(TARGET_STAGE)-y)-$(CONFIG_PARALLEL_MP) += sipi_vector.S
$(SIPI_DOTO): $(call src-to-obj,rmodules_$(ARCH-$(TARGET_STAGE)-y),src/cpu/x86/sipi_vector.S)
$(CC_rmodules_$(ARCH-$(TARGET_STAGE)-y)) $(CFLAGS_rmodules_$(ARCH-$(TARGET_STAGE)-y)) -nostdlib -r -o $@ $^
$(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_DOTO), 0,$(ARCH-$(TARGET_STAGE)-y)))
$(SIPI_BIN): $(SIPI_RMOD)
$(OBJCOPY_ramstage) -O binary $< $@
$(OBJCOPY_$(TARGET_STAGE)) -O binary $< $@
$(call src-to-obj,ramstage,$(SIPI_BIN).manual): $(SIPI_BIN)
$(call src-to-obj,$(TARGET_STAGE),$(SIPI_BIN).manual): $(SIPI_BIN)
@printf " OBJCOPY $(subst $(obj)/,,$(@))\n"
cd $(dir $<); $(OBJCOPY_rmodules_$(ARCH-ramstage-y)) -I binary $(notdir $<) $(target-objcopy) $(abspath $@)
cd $(dir $<); $(OBJCOPY_rmodules_$(ARCH-$(TARGET_STAGE)-y)) -I binary $(notdir $<) $(target-objcopy) $(abspath $@)