i945/gma.c: add native VGA init
This reuses the Intel Pineview native graphic initialization to have output on the VGA connector of i945 devices. The behavior is the same as with the vendor VBIOS BLOB. It uses the external VGA display if it is connected. Change-Id: I7eaee87d16df2e5c9ebeaaff01d36ec1aa4ea495 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/16511 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Arthur Heymans
Martin Roth
parent
7dfc8a5ebd
commit
b59bcb2d5f
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@ -77,7 +77,7 @@ static int gtt_setup(void *mmiobase)
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return 0;
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}
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static int intel_gma_init(struct northbridge_intel_i945_config *conf,
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static int intel_gma_init_lvds(struct northbridge_intel_i945_config *conf,
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unsigned int pphysbase, unsigned int piobase,
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void *pmmio, unsigned int pgfx)
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{
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@ -383,6 +383,194 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf,
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#endif
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return 0;
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}
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static int intel_gma_init_vga(struct northbridge_intel_i945_config *conf,
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unsigned int pphysbase, unsigned int piobase,
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void *pmmio, unsigned int pgfx)
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{
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int i;
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u32 hactive, vactive;
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u16 reg16;
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u32 uma_size;
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printk(BIOS_SPEW, "pmmio %x addrport %x physbase %x\n",
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(u32)pmmio, piobase, pphysbase);
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gtt_setup(pmmio);
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/* Disable VGA. */
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write32(pmmio + VGACNTRL, VGA_DISP_DISABLE);
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/* Disable pipes. */
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write32(pmmio + PIPECONF(0), 0);
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write32(pmmio + PIPECONF(1), 0);
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write32(pmmio + INSTPM, 0x800);
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vga_gr_write(0x18, 0);
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write32(pmmio + VGA0, 0x200074);
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write32(pmmio + VGA1, 0x200074);
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write32(pmmio + DSPFW3, 0x7f3f00c1 & ~PINEVIEW_SELF_REFRESH_EN);
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write32(pmmio + DSPCLK_GATE_D, 0);
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write32(pmmio + FW_BLC, 0x03060106);
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write32(pmmio + FW_BLC2, 0x00000306);
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write32(pmmio + ADPA, ADPA_DAC_ENABLE
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| ADPA_PIPE_A_SELECT
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| ADPA_USE_VGA_HVPOLARITY
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| ADPA_VSYNC_CNTL_ENABLE
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| ADPA_HSYNC_CNTL_ENABLE
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| ADPA_DPMS_ON
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);
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write32(pmmio + 0x7041c, 0x0);
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write32(pmmio + DPLL_MD(0), 0x3);
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write32(pmmio + DPLL_MD(1), 0x3);
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write32(pmmio + DSPCNTR(1), 0x1000000);
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write32(pmmio + PIPESRC(1), 0x027f01df);
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vga_misc_write(0x67);
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const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f,
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0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00,
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0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3,
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0xff
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};
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vga_cr_write(0x11, 0);
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for (i = 0; i <= 0x18; i++)
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vga_cr_write(i, cr[i]);
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// Disable screen memory to prevent garbage from appearing.
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vga_sr_write(1, vga_sr_read(1) | 0x20);
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hactive = 640;
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vactive = 400;
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mdelay(1);
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write32(pmmio + DPLL(0),
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DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL
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| DPLL_VGA_MODE_DIS
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| DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
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| 0x400601
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);
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mdelay(1);
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write32(pmmio + DPLL(0),
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DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL
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| DPLL_VGA_MODE_DIS
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| DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
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| 0x400601
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);
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write32(pmmio + ADPA, ADPA_DAC_ENABLE
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| ADPA_PIPE_A_SELECT
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| ADPA_USE_VGA_HVPOLARITY
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| ADPA_VSYNC_CNTL_ENABLE
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| ADPA_HSYNC_CNTL_ENABLE
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| ADPA_DPMS_ON
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);
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write32(pmmio + HTOTAL(0),
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((hactive - 1) << 16)
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| (hactive - 1));
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write32(pmmio + HBLANK(0),
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((hactive - 1) << 16)
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| (hactive - 1));
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write32(pmmio + HSYNC(0),
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((hactive - 1) << 16)
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| (hactive - 1));
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write32(pmmio + VTOTAL(0), ((vactive - 1) << 16)
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| (vactive - 1));
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write32(pmmio + VBLANK(0), ((vactive - 1) << 16)
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| (vactive - 1));
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write32(pmmio + VSYNC(0),
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((vactive - 1) << 16)
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| (vactive - 1));
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write32(pmmio + PF_WIN_POS(0), 0);
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write32(pmmio + PIPESRC(0), (639 << 16) | 399);
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write32(pmmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3);
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write32(pmmio + PF_WIN_SZ(0), vactive | (hactive << 16));
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write32(pmmio + PFIT_CONTROL, 0x0);
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mdelay(1);
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write32(pmmio + FDI_RX_CTL(0), 0x00002040);
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mdelay(1);
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write32(pmmio + FDI_RX_CTL(0), 0x80002050);
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write32(pmmio + FDI_TX_CTL(0), 0x00044000);
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mdelay(1);
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write32(pmmio + FDI_TX_CTL(0), 0x80044000);
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write32(pmmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
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write32(pmmio + VGACNTRL, 0x0);
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write32(pmmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888);
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mdelay(1);
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write32(pmmio + ADPA, ADPA_DAC_ENABLE
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| ADPA_PIPE_A_SELECT
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| ADPA_USE_VGA_HVPOLARITY
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| ADPA_VSYNC_CNTL_ENABLE
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| ADPA_HSYNC_CNTL_ENABLE
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| ADPA_DPMS_ON
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);
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write32(pmmio + DSPFW3, 0x7f3f00c1);
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write32(pmmio + MI_MODE, 0x200 | VS_TIMER_DISPATCH);
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write32(pmmio + CACHE_MODE_0, (0x6820 | (1 << 9)) & ~(1 << 5));
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write32(pmmio + CACHE_MODE_1, 0x380 & ~(1 << 9));
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/* Set up GTT. */
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reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), GGC);
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uma_size = 0;
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if (!(reg16 & 2)) {
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uma_size = decode_igd_memory_size((reg16 >> 4) & 7);
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printk(BIOS_DEBUG, "%dM UMA\n", uma_size >> 10);
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}
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for (i = 0; i < (uma_size - 256) / 4; i++)
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{
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outl((i << 2) | 1, piobase);
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outl(pphysbase + (i << 12) + 1, piobase + 4);
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}
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/* Clear interrupts. */
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write32(pmmio + DEIIR, 0xffffffff);
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write32(pmmio + SDEIIR, 0xffffffff);
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write32(pmmio + IIR, 0xffffffff);
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write32(pmmio + IMR, 0xffffffff);
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write32(pmmio + EIR, 0xffffffff);
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vga_textmode_init();
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/* Enable screen memory. */
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vga_sr_write(1, vga_sr_read(1) & ~0x20);
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return 0;
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}
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/* compare the header of the vga edid header */
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/* if vga is not connected it should have a correct header */
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static int vga_connected(u8 *pmmio) {
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u8 vga_edid[128];
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u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00};
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intel_gmbus_read_edid(pmmio + GMBUS0, 2, 0x50, vga_edid, 128);
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intel_gmbus_stop(pmmio + GMBUS0);
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for (int i = 0; i < 8; i++) {
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if (vga_edid[i] != header[i]) {
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printk(BIOS_DEBUG, "VGA not connected. Using LVDS display\n");
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return 0;
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}
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}
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printk(BIOS_SPEW, "VGA display connected\n");
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return 1;
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}
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#endif
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static void gma_func0_init(struct device *dev)
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@ -424,7 +612,11 @@ static void gma_func0_init(struct device *dev)
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);
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int err;
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err = intel_gma_init(conf, pci_read_config32(dev, 0x5c) & ~0xf,
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if (vga_connected(mmiobase))
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err = intel_gma_init_vga(conf, pci_read_config32(dev, 0x5c) & ~0xf,
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iobase, mmiobase, graphics_base);
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else
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err = intel_gma_init_lvds(conf, pci_read_config32(dev, 0x5c) & ~0xf,
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iobase, mmiobase, graphics_base);
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if (err == 0)
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gfx_set_init_done(1);
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