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mb/google/brya/var/craask: Add GPIO table 

Fill GPIO table for Craask.

BUG=b:229938024
TEST=emerge-nissa coreboot

Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: I3b85b4b7a68211013f5862d71c8e31ecec41c7b2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63817
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
This commit is contained in:
Tyler Wang 2022-04-25 15:37:48 +08:00 committed by Felix Held
parent 9f4ddc35d4
commit b5b2fe4946
2 changed files with 52 additions and 0 deletions
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3
src/mainboard/google/brya/variants/craask/Makefile.inc Normal file
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# SPDX-License-Identifier: GPL-2.0-only
bootblock-y += gpio.c
romstage-y += gpio.c

49
src/mainboard/google/brya/variants/craask/gpio.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <baseboard/gpio.h>
#include <baseboard/variants.h>
#include <commonlib/helpers.h>
#include <soc/gpio.h>
/* Early pad configuration in bootblock */
static const struct pad_config early_gpio_table[] = {
/* F12 : GSXDOUT ==> WWAN_RST_L */
PAD_CFG_GPO(GPP_F12, 0, DEEP),
/* H12 : UART0_RTS# ==> SD_PERST_L */
PAD_CFG_GPO(GPP_H12, 0, DEEP),
/* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */
PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
/* D6 : SRCCLKREQ1# ==> WWAN_EN */
PAD_CFG_GPO(GPP_D6, 1, DEEP),
/* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */
PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP),
/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
PAD_CFG_GPI(GPP_F18, NONE, DEEP),
/* H4 : I2C0_SDA ==> SOC_I2C_GSC_SDA */
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
/* H5 : I2C0_SCL ==> SOC_I2C_GSC_SCL */
PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
/* H10 : UART0_RXD ==> UART_SOC_RX_DBG_TX */
PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
/* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */
PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
/* H13 : UART0_CTS# ==> EN_PP3300_SD_X */
PAD_CFG_GPO(GPP_H13, 1, DEEP),
};
static const struct pad_config romstage_gpio_table[] = {
/* H12 : UART0_RTS# ==> SD_PERST_L */
PAD_CFG_GPO(GPP_H12, 1, DEEP),
};
const struct pad_config *variant_early_gpio_table(size_t *num)
{
*num = ARRAY_SIZE(early_gpio_table);
return early_gpio_table;
}
const struct pad_config *variant_romstage_gpio_table(size_t *num)
{
*num = ARRAY_SIZE(romstage_gpio_table);
return romstage_gpio_table;
}