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soc/intel/alderlake: Adding Kconfig for ADL_M PCH 

1. Add SOC_INTEL_ALDERLAKE_PCH_M option in Kconfig
2. Select number of I/O based on PCH

Signed-off-by: Varshit Pandya <varshit.b.pandya@intel.com>
Change-Id: I38783595e4b85abf5b3bec234ba01667bd9ba754
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49630
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Varshit Pandya 2021-01-18 09:44:35 +05:30 committed by Patrick Georgi
parent f4d98fdd20
commit b5df56f6f2
1 changed files with 8 additions and 0 deletions
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8
src/soc/intel/alderlake/Kconfig
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@ -3,6 +3,11 @@ config SOC_INTEL_ALDERLAKE
help
Intel Alderlake support
config SOC_INTEL_ALDERLAKE_PCH_M
bool
help
Choose this option if you have PCH-M chipset.
if SOC_INTEL_ALDERLAKE
config CPU_SPECIFIC_OPTIONS
@ -121,10 +126,12 @@ config HEAP_SIZE
config MAX_PCH_ROOT_PORTS
int
default 10 if SOC_INTEL_ALDERLAKE_PCH_M
default 12
config MAX_CPU_ROOT_PORTS
int
default 1 if SOC_INTEL_ALDERLAKE_PCH_M
default 3
config MAX_ROOT_PORTS
@ -133,6 +140,7 @@ config MAX_ROOT_PORTS
config MAX_PCIE_CLOCKS
int
default 10 if SOC_INTEL_ALDERLAKE_PCH_M
default 12
config SMM_TSEG_SIZE