intel/broadwell: Don't select MONOTONIC_TIMER_MSR

That's a Haswell exclusive, used nowhere else, but confusing
when hunting for the monotonic timer used on that SoC.

Change-Id: I60ec523e54e5af0d2a418bcb9145de452a3a4ea9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10034
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Patrick Georgi 2015-04-29 20:44:06 +02:00 committed by Patrick Georgi
parent e3f880e4d8
commit b5e1984594
3 changed files with 0 additions and 8 deletions

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@ -16,7 +16,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_SMI_HANDLER select HAVE_SMI_HANDLER
select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_CHROMEOS
select EXTERNAL_MRC_BLOB select EXTERNAL_MRC_BLOB
select MONOTONIC_TIMER_MSR
select CHROMEOS_RAMOOPS_DYNAMIC select CHROMEOS_RAMOOPS_DYNAMIC
select INTEL_INT15 select INTEL_INT15
select CHROMEOS_VBNV_CMOS select CHROMEOS_VBNV_CMOS

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@ -10,7 +10,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_SMI_HANDLER select HAVE_SMI_HANDLER
select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_CHROMEOS
select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_HAS_NATIVE_VGA_INIT
select MONOTONIC_TIMER_MSR
select INTEL_INT15 select INTEL_INT15
select CHROMEOS_RAMOOPS_DYNAMIC select CHROMEOS_RAMOOPS_DYNAMIC

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@ -174,12 +174,6 @@ config RESET_ON_INVALID_RAMSTAGE_CACHE
when the ramstage cache is invalid. If selected the system will when the ramstage cache is invalid. If selected the system will
reset otherwise the ramstage will be reloaded from cbfs. reset otherwise the ramstage will be reloaded from cbfs.
config MONOTONIC_TIMER_MSR
def_bool y
select HAVE_MONOTONIC_TIMER
help
Provide a monotonic timer using the 24MHz MSR counter.
config INTEL_PCH_UART_CONSOLE config INTEL_PCH_UART_CONSOLE
bool "Use Serial IO UART for console" bool "Use Serial IO UART for console"
default n default n