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mb/google/dedede/variants/drawcia: Update TSR1 passive trip temperature 

Update TSR1 passive trip temperature

BUG=b:169691800
BRANCH=None
TEST=Built and tested on dedede system

Change-Id: I172391daca981d5591fa9cc5eacad92521dd0dc5
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45859
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
This commit is contained in:
Sumeet R Pawnikar 2020-09-30 10:27:01 +05:30 committed by Karthik Ramasubramanian
parent 833b5b33d2
commit b5e4e34418
1 changed files with 1 additions and 1 deletions
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src/mainboard/google/dedede/variants/drawcia/overridetree.cb
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@ -75,7 +75,7 @@ chip soc/intel/jasperlake
register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 80, 1000)"
register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 70, 4000)"
register "policies.passive[2]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 75, 1000)"
register "policies.passive[2]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 51, 1000)"
register "policies.passive[3]" = "DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 75, 5000)"
register "policies.passive[4]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 60, 1000)"