drivers/gic: Remove unnecessary code
On AArch64 platforms, GIC initialization is generally the job of Trusted Firmware and shouldn't be necessary in coreboot. Only the ancient T210 platform (which was started before we had decided on using Trusted Firmware) calls this code, and even there they have a comment wondering "do we still need this?". I'm just gonna assume (without testing because that board is ancient and I'm lazy) that they don't, and that the TF GIC initialization[1] is sufficient here. Remove this obsolete driver. [1] https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3ff448/plat/nvidia/tegra/soc/t210/plat_setup.c#259 Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I3e9d90039dd27cb3a13f830ba21fc5cc7a70abe2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57818 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Julius Werner
parent
ee760b4be8
commit
b5e7bd2a58
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@ -1,4 +0,0 @@
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config GIC
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def_bool n
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help
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This option enables GIC support, the ARM generic interrupt controller.
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@ -1 +0,0 @@
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ramstage-$(CONFIG_GIC) += gic.c
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@ -1,148 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <arch/cpu.h>
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#include <device/mmio.h>
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#include <console/console.h>
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#include <gic.h>
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#include <stddef.h>
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#include "gic.h"
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enum {
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ENABLE_GRP0 = 0x1 << 0,
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ENABLE_GRP1 = 0x1 << 1,
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FIQ_BYP_DIS_GRP0 = 0x1 << 5,
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IRQ_BYP_DIS_GRP0 = 0x1 << 6,
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FIQ_BYP_DIS_GRP1 = 0x1 << 7,
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IRQ_BYP_DIS_GRP1 = 0x1 << 8,
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};
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struct gic {
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struct gicd_mmio *gicd;
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struct gicc_mmio *gicc;
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size_t num_interrupts;
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unsigned int version;
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unsigned int security_extensions;
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};
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static struct gic *gic_get(void)
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{
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static struct gic gic;
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if (gic.gicd == NULL) {
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uint32_t typer;
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gic.gicd = gicd_base();
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gic.gicc = gicc_base();
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typer = read32(&gic.gicd->typer);
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gic.num_interrupts = 32 * ((typer & 0x1f) + 1);
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gic.security_extensions = !!(typer & (1 << 10));
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gic.version = (read32(&gic.gicd->icpidr2) & 0xf0) >> 4;
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printk(BIOS_DEBUG, "GICv%d - %zu ints %s GICD=%p GICC=%p\n",
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gic.version, gic.num_interrupts,
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gic.security_extensions ? "SecExtn" : "",
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gic.gicd, gic.gicc);
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}
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return &gic;
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}
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static inline uint32_t gic_read(uint32_t *base)
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{
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return read32(base);
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}
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static inline void gic_write(uint32_t *base, uint32_t val)
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{
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write32(base, val);
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}
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static void gic_write_regs(uint32_t *base, size_t num_regs, uint32_t val)
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{
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size_t i;
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for (i = 0; i < num_regs; i++)
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gic_write(base++, val);
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}
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static void gic_write_banked_regs(uint32_t *base, size_t interrupts_per_reg,
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uint32_t val)
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{
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/* 1st 32 interrupts are banked per CPU. */
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gic_write_regs(base, 32 / interrupts_per_reg, val);
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}
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void gic_init(void)
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{
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struct gic *gic;
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struct gicd_mmio *gicd;
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struct gicc_mmio *gicc;
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uint32_t cpu_mask;
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gic = gic_get();
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gicd = gic->gicd;
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gicc = gic->gicc;
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/* Enable Group 0 and Group 1 in GICD -- banked regs. */
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gic_write(&gicd->ctlr, ENABLE_GRP0 | ENABLE_GRP1);
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/* Enable Group 0 and Group 1 in GICC and enable all priroity levels. */
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gic_write(&gicc->ctlr, ENABLE_GRP0 | ENABLE_GRP1);
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gic_write(&gicc->pmr, 1 << 7);
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cpu_mask = 1 << smp_processor_id();
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cpu_mask |= cpu_mask << 8;
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cpu_mask |= cpu_mask << 16;
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/* Only write banked registers for secondary CPUs. */
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if (smp_processor_id()) {
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gic_write_banked_regs(&gicd->itargetsr[0], 4, cpu_mask);
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/* Put interrupts into Group 1. */
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gic_write_banked_regs(&gicd->igroupr[0], 32, ~0x0);
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/* Allow Non-secure access to everything. */
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gic_write_banked_regs(&gicd->nsacr[0], 16, ~0x0);
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return;
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}
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/* All interrupts routed to processors that execute this function. */
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gic_write_regs(&gicd->itargetsr[0], gic->num_interrupts / 4, cpu_mask);
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/* Put all interrupts into Gropup 1. */
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gic_write_regs(&gicd->igroupr[0], gic->num_interrupts / 32, ~0x0);
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/* Allow Non-secure access to everything. */
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gic_write_regs(&gicd->nsacr[0], gic->num_interrupts / 16, ~0x0);
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}
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void gic_disable(void)
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{
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struct gic *gic;
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struct gicc_mmio *gicc;
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gic = gic_get();
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gicc = gic->gicc;
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/* Disable secure, non-secure interrupts. */
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uint32_t val = gic_read(&gicc->ctlr);
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val &= ~(ENABLE_GRP0 | ENABLE_GRP1);
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/*
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* Enable the IRQ/FIQ BypassDisable bits to bypass the IRQs.
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* So the CPU can wake up from power gating state when the GIC
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* was disabled.
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*/
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val |= FIQ_BYP_DIS_GRP0 | IRQ_BYP_DIS_GRP0 |
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FIQ_BYP_DIS_GRP1 | IRQ_BYP_DIS_GRP1;
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gic_write(&gicc->ctlr, val);
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}
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void gic_enable(void)
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{
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struct gic *gic;
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struct gicc_mmio *gicc;
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gic = gic_get();
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gicc = gic->gicc;
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/* Enable secure, non-secure interrupts. */
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uint32_t val = gic_read(&gicc->ctlr);
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val |= (ENABLE_GRP0 | ENABLE_GRP1);
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gic_write(&gicc->ctlr, val);
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}
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@ -1,61 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef DRIVERS_GIC_H
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#define DRIVERS_GIC_H
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#include <stdint.h>
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#define NR(start, end) (((end) - (start)) / sizeof(uint32_t))
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struct gicd_mmio {
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uint32_t ctlr; /* 0x000 - 0x003 */
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uint32_t typer; /* 0x004 - 0x007 */
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uint32_t iidr; /* 0x008 - 0x00b */
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uint32_t reserved_1[NR(0xc, 0x80)]; /* 0x00c - 0x07f */
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uint32_t igroupr[NR(0x80, 0x100)]; /* 0x080 - 0x0ff */
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uint32_t isenabler[NR(0x100, 0x180)]; /* 0x100 - 0x17f */
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uint32_t icenabler[NR(0x180, 0x200)]; /* 0x180 - 0x1ff */
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uint32_t ispendr[NR(0x200, 0x280)]; /* 0x200 - 0x27f */
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uint32_t icpendr[NR(0x280, 0x300)]; /* 0x280 - 0x2ff */
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uint32_t isactiver[NR(0x300, 0x380)]; /* 0x300 - 0x37f */
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uint32_t icactiver[NR(0x380, 0x400)]; /* 0x380 - 0x3ff */
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uint32_t ipriorityr[NR(0x400, 0x7fc)]; /* 0x400 - 0x7fb */
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uint32_t reserved_2[NR(0x7fc, 0x800)]; /* 0x7fc - 0x7ff */
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uint32_t itargetsr[NR(0x800, 0xbfc)]; /* 0x800 - 0xbfb */
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uint32_t reserved_3[NR(0xbfc, 0xc00)]; /* 0xbfc - 0x2ff */
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uint32_t icfgr[NR(0xc00, 0xd00)]; /* 0xc00 - 0xcff */
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uint32_t reserved_4[NR(0xd00, 0xe00)]; /* 0xd00 - 0xdff */
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uint32_t nsacr[NR(0xe00, 0xf00)]; /* 0xe00 - 0xeff */
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uint32_t sgir; /* 0xf00 - 0xf03 */
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uint32_t reserved_5[NR(0xf04, 0xf10)]; /* 0xf04 - 0xf0f */
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uint32_t cpendsgir[NR(0xf10, 0xf20)]; /* 0xf10 - 0xf1f */
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uint32_t spendsgir[NR(0xf20, 0xf30)]; /* 0xf20 - 0xf2f */
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uint32_t reserved_6[NR(0xf30, 0xfe8)]; /* 0xf30 - 0xfe7 */
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uint32_t icpidr2; /* 0xfe8 - 0xfeb */
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uint32_t reserved_7[NR(0xfec, 0x1000)]; /* 0xfec - 0xfff */
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};
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struct gicc_mmio {
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uint32_t ctlr; /* 0x000 - 0x003 */
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uint32_t pmr; /* 0x004 - 0x007 */
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uint32_t bpr; /* 0x008 - 0x00b */
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uint32_t iar; /* 0x00c - 0x00f */
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uint32_t eoir; /* 0x010 - 0x013 */
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uint32_t rpr; /* 0x014 - 0x017 */
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uint32_t hppir; /* 0x018 - 0x01b */
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uint32_t apbr; /* 0x01c - 0x01f */
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uint32_t aiar; /* 0x020 - 0x023 */
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uint32_t aeoir; /* 0x024 - 0x027 */
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uint32_t ahppir; /* 0x028 - 0x02b */
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uint32_t resered_1[NR(0x2c, 0xd0)]; /* 0x02c - 0x0cf */
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uint32_t apr[NR(0xd0, 0xe0)]; /* 0x0d0 - 0x0df */
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uint32_t nsapr[NR(0xe0, 0xf0)]; /* 0x0e0 - 0x0ef */
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uint32_t resered_2[NR(0xf0, 0xfc)]; /* 0x0f0 - 0x0fb */
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uint32_t iidr; /* 0x0fc - 0x0ff */
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uint32_t reserved_3[NR(0x100, 0x1000)]; /* 0x100 - 0xfff */
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uint32_t dir; /* 0x1000 - 0x1003 */
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};
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#undef NR
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#endif /* DRIVERS_GIC_H */
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@ -1,26 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef GIC_H
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#define GIC_H
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#if CONFIG(GIC)
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/* Initialize the GIC on the currently processor, including GICD and GICC. */
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void gic_init(void);
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void gic_disable(void);
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void gic_enable(void);
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/* Return a pointer to the base of the GIC distributor mmio region. */
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void *gicd_base(void);
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/* Return a pointer to the base of the GIC CPU mmio region. */
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void *gicc_base(void);
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#else /* CONFIG_GIC */
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static inline void gic_init(void) {}
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static inline void gic_disable(void) {}
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#endif /* CONFIG_GIC */
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#endif /* GIC_H */
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@ -6,7 +6,6 @@ config SOC_NVIDIA_TEGRA210
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select ARCH_VERSTAGE_ARMV4
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select ARCH_ROMSTAGE_ARMV4
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select ARCH_RAMSTAGE_ARMV8_64
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select GIC
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select HAVE_UART_SPECIAL
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select ARM64_USE_ARM_TRUSTED_FIRMWARE
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select GENERIC_GPIO_LIB
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@ -79,7 +79,6 @@ ramstage-y += i2c6.c
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ramstage-y += ape.c
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ramstage-y += power.c
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ramstage-y += dma.c
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ramstage-y += gic.c
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ramstage-y += monotonic_timer.c
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ramstage-y += padconfig.c
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ramstage-y += funitcfg.c
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@ -1,14 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <gic.h>
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#include <soc/addressmap.h>
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void *gicd_base(void)
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{
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return (void *)(uintptr_t)TEGRA_GICD_BASE;
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}
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void *gicc_base(void)
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{
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return (void *)(uintptr_t)TEGRA_GICC_BASE;
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}
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@ -5,7 +5,6 @@
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#include <cbmem.h>
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#include <console/console.h>
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#include <device/mmio.h>
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#include <gic.h>
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#include <soc/addressmap.h>
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#include <soc/clock.h>
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#include <soc/mmu_operations.h>
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@ -41,9 +40,6 @@ static void mselect_enable_wrap(void)
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void ramstage_entry(void);
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void ramstage_entry(void)
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{
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/* TODO: Is this still needed? */
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gic_init();
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/* TODO: Move arch timer setup to BL31? */
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arm64_arch_timer_init();
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