GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mb/google/brya/var/taniks: Remove unused temp sensor setting 

Rwmove temp sensor 3 for taniks since we do not use it.

BUG=b:265075696
TEST=emerge-brya coreboot, flash to DUT and will not see error messages

Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: Ib2c0cc8f1b2e65616c71d66632144ac89ca09fa1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73718
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This commit is contained in:
Joey Peng 2023-03-14 14:20:55 +08:00 committed by Martin L Roth
parent 3e7008df95
commit b5fd92a14e
1 changed files with 0 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
src/mainboard/google/brya/variants/taniks/overridetree.cb
View File

@ -120,7 +120,6 @@ chip soc/intel/alderlake
register "options.tsr[0].desc" = ""DRAM_SOC"" register "options.tsr[0].desc" = ""DRAM_SOC""
register "options.tsr[1].desc" = ""Ambient"" register "options.tsr[1].desc" = ""Ambient""
register "options.tsr[2].desc" = ""Charger"" register "options.tsr[2].desc" = ""Charger""
register "options.tsr[3].desc" = ""WWAN""
# TODO: below values are initial reference values only # TODO: below values are initial reference values only
## Active Policy ## Active Policy
@ -155,16 +154,6 @@ chip soc/intel/alderlake
TEMP_PCT(42, 40), TEMP_PCT(42, 40),
} }
}, },
[3] = {
.target = DPTF_TEMP_SENSOR_3,
.thresholds = {
TEMP_PCT(60, 69),
TEMP_PCT(56, 50),
TEMP_PCT(52, 50),
TEMP_PCT(46, 40),
TEMP_PCT(42, 40),
}
}
}" }"
## Passive Policy ## Passive Policy
@ -173,7 +162,6 @@ chip soc/intel/alderlake
[1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 90, 6000), [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 90, 6000),
[2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 90, 6000), [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 90, 6000),
[3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 90, 6000), [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 90, 6000),
[4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 90, 6000),
}" }"
## Critical Policy ## Critical Policy
@ -182,7 +170,6 @@ chip soc/intel/alderlake
[1] = DPTF_CRITICAL(TEMP_SENSOR_0, 100, SHUTDOWN), [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 100, SHUTDOWN),
[2] = DPTF_CRITICAL(TEMP_SENSOR_1, 100, SHUTDOWN), [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 100, SHUTDOWN),
[3] = DPTF_CRITICAL(TEMP_SENSOR_2, 100, SHUTDOWN), [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 100, SHUTDOWN),
[4] = DPTF_CRITICAL(TEMP_SENSOR_3, 100, SHUTDOWN),
}" }"
register "controls.power_limits" = "{ register "controls.power_limits" = "{