GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

nb/intel/ironlake: Print MCH dev/revision IDs and CAPID 

Given the lack of documentation for this platform, having this info
in coreboot logs (e.g. from board_status) can be pretty useful.

Change-Id: I6a743c1efc1b6da71589460a69bfe4785e3e77a2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49576
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Angel Pons 2021-01-16 16:33:48 +01:00 committed by Patrick Georgi
parent d0a62c667d
commit b600d41c3f
1 changed files with 8 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
src/northbridge/intel/ironlake/raminit.c
View File

@ -1480,10 +1480,14 @@ static void collect_system_info(struct raminfo *info)
info->memory_reserved_for_heci_mb = intel_early_me_uma_size();
}
for (i = 0; i < 3; i++)
gav(capid0[i] =
pci_read_config32(NORTHBRIDGE, CAPID0 | (i << 2)));
gav(info->revision = pci_read_config8(NORTHBRIDGE, PCI_REVISION_ID));
for (i = 0; i < 3; i++) {
capid0[i] = pci_read_config32(NORTHBRIDGE, CAPID0 | (i << 2));
printk(BIOS_DEBUG, "CAPID0[%d] = 0x%08x\n", i, capid0[i]);
}
info->revision = pci_read_config8(NORTHBRIDGE, PCI_REVISION_ID);
printk(BIOS_DEBUG, "Revision ID: 0x%x\n", info->revision);
printk(BIOS_DEBUG, "Device ID: 0x%x\n", pci_read_config16(NORTHBRIDGE, PCI_DEVICE_ID));
info->max_supported_clock_speed_index = (~capid0[1] & 7);
if ((capid0[1] >> 11) & 1)