soc/intel/apollolake: Enable SSDT for fast SPI controller
Since the fast SPI controller is hidden on Apollo Lake the OS cannot probe it and is therefore unaware of the reserved resources assigned in coreboot. Select 'FAST_SPI_GENERATE_SSDT' to enable SSDT creation to report the reserved resources to the OS. Change-Id: I23e77a0a01141dc4f299988d19509e6df555a654 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64419 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
This commit is contained in:
parent
ea2c1d357c
commit
b60e69bde8
|
@ -37,6 +37,7 @@ config CPU_SPECIFIC_OPTIONS
|
||||||
select SOC_INTEL_COMMON_NHLT
|
select SOC_INTEL_COMMON_NHLT
|
||||||
# Misc options
|
# Misc options
|
||||||
select CACHE_MRC_SETTINGS
|
select CACHE_MRC_SETTINGS
|
||||||
|
select FAST_SPI_GENERATE_SSDT
|
||||||
select FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS
|
select FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS
|
||||||
select FSP_STATUS_GLOBAL_RESET_REQUIRED_5
|
select FSP_STATUS_GLOBAL_RESET_REQUIRED_5
|
||||||
select GENERIC_GPIO_LIB
|
select GENERIC_GPIO_LIB
|
||||||
|
|
Loading…
Reference in New Issue