amd/stoneyridge: Enable SMM in TSEG
Add necessary features to allow mp_init_with_smm() to install and relocate an SMM handler. SMM region functions are added to easily identify the SMM attributes. Adjust the neighboring cbmem_top() rounding downward to better reflect the default TSEG size. Add relocation attributes to be set by each core a relocation handler. Modify the definition of smi_southbridge_handler() to match TSEG prototype. BUG=b:62103112 Change-Id: I4dc03ed27d0d109ab919a4f0861de9c7420d03ce Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21501 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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@ -51,6 +51,8 @@ config CPU_SPECIFIC_OPTIONS
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select BOOTBLOCK_CONSOLE
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select RELOCATABLE_MODULES
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select PARALLEL_MP
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select HAVE_SMI_HANDLER
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select SMM_TSEG
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config VBOOT
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select AMDFW_OUTSIDE_CBFS
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@ -286,6 +288,10 @@ config SMM_TSEG_SIZE
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default 0x800000 if SMM_TSEG && HAVE_SMI_HANDLER
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default 0x0
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config SMM_RESERVED_SIZE
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hex
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default 0x100000
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config ACPI_CPU_STRING
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string
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default "\\_PR.P%03d"
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@ -14,14 +14,29 @@
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* GNU General Public License for more details.
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*/
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#include <cpu/cpu.h>
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#include <cpu/x86/mp.h>
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/msr.h>
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#include <cpu/amd/amdfam15.h>
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#include <device/device.h>
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#include <soc/pci_devs.h>
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#include <soc/cpu.h>
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#include <soc/northbridge.h>
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#include <soc/smi.h>
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#include <console/console.h>
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/*
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* MP and SMM loading initialization.
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*/
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struct smm_relocation_attrs {
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uint32_t smbase;
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uint32_t tseg_base;
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uint32_t tseg_mask;
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};
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static struct smm_relocation_attrs relo_attrs;
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/*
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* Do essential initialization tasks before APs can be fired up -
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*
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@ -41,9 +56,50 @@ static int get_cpu_count(void)
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return (pci_read_config16(nb, D18F0_CPU_CNT) & CPU_CNT_MASK) + 1;
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}
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static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
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size_t *smm_save_state_size)
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{
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void *smm_base;
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size_t smm_size;
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void *handler_base;
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size_t handler_size;
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/* Initialize global tracking state. */
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smm_region_info(&smm_base, &smm_size);
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smm_subregion(SMM_SUBREGION_HANDLER, &handler_base, &handler_size);
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relo_attrs.smbase = (uint32_t)smm_base;
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relo_attrs.tseg_base = relo_attrs.smbase;
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relo_attrs.tseg_mask = ALIGN_DOWN(~(smm_size - 1), 128 * KiB);
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relo_attrs.tseg_mask |= SMM_TSEG_WB | SMM_TSEG_VALID;
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*perm_smbase = (uintptr_t)handler_base;
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*perm_smsize = handler_size;
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*smm_save_state_size = sizeof(amd64_smm_state_save_area_t);
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}
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static void relocation_handler(int cpu, uintptr_t curr_smbase,
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uintptr_t staggered_smbase)
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{
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msr_t tseg_base, tseg_mask;
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amd64_smm_state_save_area_t *smm_state;
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tseg_base.lo = relo_attrs.tseg_base;
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tseg_base.hi = 0;
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wrmsr(MSR_TSEG_BASE, tseg_base);
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tseg_mask.lo = relo_attrs.tseg_mask;
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tseg_mask.hi = ((1 << (cpu_phys_address_size() - 32)) - 1);
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wrmsr(MSR_SMM_MASK, tseg_mask);
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smm_state = (void *)(SMM_AMD64_SAVE_STATE_OFFSET + curr_smbase);
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smm_state->smbase = staggered_smbase;
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}
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static const struct mp_ops mp_ops = {
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.pre_mp_init = pre_mp_init,
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.get_cpu_count = get_cpu_count,
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.get_smm_info = get_smm_info,
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.relocation_handler = relocation_handler,
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.post_mp_init = enable_smi_generation,
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};
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void stoney_init_cpus(struct device *dev)
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@ -2,6 +2,7 @@
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015 Advanced Micro Devices, Inc.
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* Copyright (C) 2015 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -30,6 +31,27 @@
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# define DRAM_HOIST_VALID (1 << 1)
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# define DRAM_HOLE_VALID (1 << 0)
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enum {
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/* SMM handler area. */
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SMM_SUBREGION_HANDLER,
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/* SMM cache region. */
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SMM_SUBREGION_CACHE,
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/* Chipset specific area. */
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SMM_SUBREGION_CHIPSET,
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/* Total sub regions supported. */
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SMM_SUBREGION_NUM,
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};
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/*
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* Fills in the arguments for the entire SMM region covered by chipset
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* protections. e.g. TSEG.
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*/
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void smm_region_info(void **start, size_t *size);
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/*
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* Fills in the start and size for the requested SMM subregion. Returns
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* 0 on susccess, < 0 on failure.
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*/
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int smm_subregion(int sub, void **start, size_t *size);
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void domain_enable_resources(device_t dev);
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void domain_read_resources(device_t dev);
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void domain_set_resources(device_t dev);
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@ -415,6 +415,8 @@ void domain_set_resources(device_t dev)
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u32 hole;
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int idx;
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struct bus *link;
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void *tseg_base;
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size_t tseg_size;
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pci_tolm = 0xffffffffUL;
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for (link = dev->link_list ; link ; link = link->next)
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@ -505,6 +507,12 @@ void domain_set_resources(device_t dev)
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*/
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mmio_resource(dev, 0xa0000, 0xa0000 / KiB, 0x20000 / KiB);
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reserved_ram_resource(dev, 0xc0000, 0xc0000 / KiB, 0x40000 / KiB);
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/* Reserve TSEG */
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smm_region_info(&tseg_base, &tseg_size);
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idx += 0x10;
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reserved_ram_resource(dev, idx, (unsigned long)tseg_base/KiB,
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tseg_size/KiB);
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}
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/*********************************************************************
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@ -1,6 +1,8 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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@ -13,11 +15,13 @@
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#define __SIMPLE_DEVICE__
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#include <assert.h>
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#include <stdint.h>
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#include <arch/io.h>
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#include <cpu/x86/msr.h>
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#include <cpu/amd/mtrr.h>
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#include <cbmem.h>
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#include <soc/northbridge.h>
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#define CBMEM_TOP_SCRATCHPAD 0x78
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@ -41,7 +45,54 @@ void *cbmem_top(void)
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if (!tom.lo)
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return 0;
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else
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/* 16MB alignment to keep MTRR usage low */
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/* 8MB alignment to keep MTRR usage low */
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return (void *)ALIGN_DOWN(restore_top_of_low_cacheable()
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- CONFIG_SMM_TSEG_SIZE, 16*MiB);
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- CONFIG_SMM_TSEG_SIZE, 8*MiB);
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}
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static uintptr_t smm_region_start(void)
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{
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return (uintptr_t)cbmem_top();
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}
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static size_t smm_region_size(void)
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{
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return CONFIG_SMM_TSEG_SIZE;
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}
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void smm_region_info(void **start, size_t *size)
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{
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*start = (void *)smm_region_start();
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*size = smm_region_size();
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}
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int smm_subregion(int sub, void **start, size_t *size)
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{
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uintptr_t sub_base;
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size_t sub_size;
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const size_t cache_size = CONFIG_SMM_RESERVED_SIZE;
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sub_base = smm_region_start();
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sub_size = smm_region_size();
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assert(sub_size > CONFIG_SMM_RESERVED_SIZE);
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switch (sub) {
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case SMM_SUBREGION_HANDLER:
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/* Handler starts at the base of TSEG. */
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sub_size -= cache_size;
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break;
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case SMM_SUBREGION_CACHE:
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/* External cache is in the middle of TSEG. */
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sub_base += sub_size - cache_size;
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sub_size = cache_size;
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break;
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default:
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return -1;
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}
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*start = (void *)sub_base;
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*size = sub_size;
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return 0;
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}
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@ -109,8 +109,7 @@ static void process_smi_0x90(void)
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smi_write32(0x90, status);
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}
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void southbridge_smi_handler(unsigned int node,
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smm_state_save_area_t *state_save)
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void southbridge_smi_handler(void)
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{
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const uint16_t smi_src = smi_read16(0x94);
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