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google/cyan: Configure EC_IN_RW signal as gpio input 

BUG=chrome-os-partner:42881
BRANCH=None
TEST=Using ctrl-d in recovery mode to switch to dev mode works.

Change-Id: Iefbd11d435c4beb570875d4835a085b194d1d1e8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: be172409792a224855b1d31621f23d1969d319b9
Original-Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Original-Change-Id: Icf57dfc4cc258aa2cba341f40d285f8c843aace5
Original-Reviewed-on: https://chromium-review.googlesource.com/286612
Original-Commit-Queue: Hannah Williams <hannah.williams@intel.com>
Original-Tested-by: Hannah Williams <hannah.williams@intel.com>
Original-Reviewed-by: Shawn N <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/11013
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Hannah Williams 2015-07-18 16:04:21 -07:00 committed by Patrick Georgi
parent f4e9eb9aba
commit b61ed3550b
1 changed files with 1 additions and 1 deletions
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2
src/mainboard/google/cyan/gpio.c
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@ -131,7 +131,7 @@ static const struct soc_gpio_map gpsw_gpio_map[] = {
GPIO_INPUT_NO_PULL,/* 67 I2C3_SCL,RAMID1 */ GPIO_INPUT_NO_PULL,/* 67 I2C3_SCL,RAMID1 */
GPIO_OUT_HIGH, /* 75 SATA_GP0 */ GPIO_OUT_HIGH, /* 75 SATA_GP0 */
GPIO_NC, /* 76 GPI SATA_GP1 */ GPIO_NC, /* 76 GPI SATA_GP1 */
Native_M1, /* 77 SATA_LEDN */ GPIO_INPUT_PU_20K, /* 77 SATA_LEDN, EC_IN_RW */
GPIO_NC, /* 78 HSIC AUX1 / SV Mode/ SATA_GP2 */ GPIO_NC, /* 78 HSIC AUX1 / SV Mode/ SATA_GP2 */
Native_M1, /* 79 MF_SMB_ALERTB */ Native_M1, /* 79 MF_SMB_ALERTB */
GPIO_INPUT_NO_PULL, /* 80 SATA_GP3,RAMID0 */ GPIO_INPUT_NO_PULL, /* 80 SATA_GP3,RAMID0 */