mainboard/google/puff: Enable pcie7 ep in dt

Missing bus init for RTL8111H ethernet chip hanging on bus.

V.2: Include admendments from Kangheui.

BRANCH=none
BUG=b:146437819
TEST=./util/abuild/abuild -p none -t google/hatch -x -a

Change-Id: I22aba312f183ea05eeb81d326ca0c05ce340a2e8
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

src/mainboard/google/hatch/Kconfig

@@ -22,6 +22,8 @@ config BOARD_GOOGLE_BASEBOARD_HATCH
 	select MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE
 	select SOC_INTEL_COMETLAKE
 	select SYSTEM_TYPE_LAPTOP
+	select RT8168_GET_MAC_FROM_VPD if BOARD_GOOGLE_PUFF
+	select RT8168_SET_LED_MODE if BOARD_GOOGLE_PUFF
 
 if BOARD_GOOGLE_BASEBOARD_HATCH
 

src/mainboard/google/hatch/variants/puff/overridetree.cb

@@ -103,6 +103,13 @@ chip soc/intel/cannonlake
 		},
 	}"
 
+	# PCIe port 7 for LAN
+	register "PcieRpEnable[6]" = "1"
+	register "PcieRpLtrEnable[6]" = "1"
+	# Uses CLK SRC 0
+	register "PcieClkSrcUsage[0]" = "6"
+	register "PcieClkSrcClkReq[0]" = "0"
+
 	# GPIO for SD card detect
 	register "sdcard_cd_gpio" = "vSD3_CD_B"
 
@@ -134,6 +141,7 @@ chip soc/intel/cannonlake
 			end
 		end #I2C #4
 		device pci 1a.0 on  end # eMMC
+		device pci 1c.6 on  end # PCI Express Port 7, RTL8111H Ethernet NIC.
 		device pci 1e.3 off end # GSPI #1
 	end