soc/intel/tigerlake: Select PLATFORM_USES_FSP2_2

This patch performs below operations
1. Add support for FSP 2.2
2. Set EnableMultiPhaseSiliconInit to ensure bootloader can call
FspMultiPhaseSiInit() API.
3. Provide placeholder to perform require chipset programming (example TCSS)
before calling FspMultiPhaseSiInit() API.

Change-Id: I15252d2db3f8e75d430b84e86cc5141225a3f981
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41729
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
This commit is contained in:
Subrata Banik 2020-05-26 18:33:22 +05:30 committed by Furquan Shaikh
parent f6b2e6f836
commit b622d4b27b
2 changed files with 21 additions and 1 deletions

View File

@ -32,7 +32,7 @@ config CPU_SPECIFIC_OPTIONS
select PARALLEL_MP select PARALLEL_MP
select PARALLEL_MP_AP_WORK select PARALLEL_MP_AP_WORK
select MICROCODE_BLOB_UNDISCLOSED select MICROCODE_BLOB_UNDISCLOSED
select PLATFORM_USES_FSP2_1 select PLATFORM_USES_FSP2_2
select FSP_PEIM_TO_PEIM_INTERFACE select FSP_PEIM_TO_PEIM_INTERFACE
select REG_SCRIPT select REG_SCRIPT
select SMP select SMP

View File

@ -327,9 +327,29 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
} }
/* EnableMultiPhaseSiliconInit for running MultiPhaseSiInit */
params->EnableMultiPhaseSiliconInit = 1;
mainboard_silicon_init_params(params); mainboard_silicon_init_params(params);
} }
/*
* Callbacks for SoC/Mainboard specific overrides for FspMultiPhaseSiInit
* This platform supports below MultiPhaseSIInit Phase(s):
* Phase | FSP return point | Purpose
* ------- + ------------------------------------------------ + -------------------------------
* 1 | After TCSS initialization completed | for TCSS specific init
*/
void platform_fsp_multi_phase_init_cb(uint32_t phase_index)
{
switch (phase_index) {
case 1:
/* TCSS specific initialization here */
break;
default:
break;
}
}
/* Mainboard GPIO Configuration */ /* Mainboard GPIO Configuration */
__weak void mainboard_silicon_init_params(FSP_S_CONFIG *params) __weak void mainboard_silicon_init_params(FSP_S_CONFIG *params)
{ {