From b6319c1121332551a51a9ef7d88c3e7ed8d0670d Mon Sep 17 00:00:00 2001 From: Rizwan Qureshi Date: Thu, 19 Nov 2015 16:27:03 +0530 Subject: [PATCH] intel/skylake: Enable SkipMpInit token This patch helps to enable SkipMpInit token of FSP SiliconInit UPD BRANCH=none BUG=chrome-os-partner:44805 TEST=Build and booted in kunimitsu with SkipMpInit enabled from CB. CQ-DEPEND=CL:310869 Change-Id: I43377e4b8adadf42091a9387883363fdfbab4c1b Signed-off-by: Patrick Georgi Original-Commit-Id: b7962273fd1a591cfe9a658f49ebc7d23bcad577 Original-Change-Id: I977d2d39c283d74f1aa9033c8aa60dc652735019 Original-Signed-off-by: Barnali Sarkar Original-Signed-off-by: Rizwan Qureshi Original-Reviewed-on: https://chromium-review.googlesource.com/310192 Original-Reviewed-by: Aaron Durbin Reviewed-on: https://review.coreboot.org/12943 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/soc/intel/skylake/chip.c | 2 ++ src/soc/intel/skylake/chip.h | 1 + 2 files changed, 3 insertions(+) diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 951e461ee1..ec5128a50c 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -345,6 +345,8 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params) params->SerialIrqConfigSirqMode = config->SerialIrqConfigSirqMode; params->SerialIrqConfigStartFramePulse = config->SerialIrqConfigStartFramePulse; + params->SkipMpInit = config->SkipMpInit; + /* Show SPI controller if enabled in devicetree.cb */ dev = dev_find_slot(0, PCH_DEVFN_SPI); params->ShowSpiController = dev->enabled; diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 94a2b73dcf..2a1980c8a3 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -324,6 +324,7 @@ struct soc_intel_skylake_config { * Values: 0: PchSfpw4Clk, 1: PchSfpw6Clk, 2; PchSfpw8Clk. */ u8 SerialIrqConfigStartFramePulse; + u8 SkipMpInit; }; typedef struct soc_intel_skylake_config config_t;