Remove the building warnings.
Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5272 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Zheng Bao
Zheng Bao
parent
c8c09bb239
commit
b63bdbe29b
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@ -107,12 +107,12 @@ void static rs780_config_misc_clk(device_t nb_dev)
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set_htiu_enable_bits(nb_dev, 0x05, 7 << 8, 7 << 8);
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}
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u32 get_vid_did(device_t dev)
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static u32 get_vid_did(device_t dev)
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{
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return pci_read_config32(dev, 0);
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}
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void rs780_nb_pci_table(device_t nb_dev)
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static void rs780_nb_pci_table(device_t nb_dev)
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{ /* NBPOR_InitPOR function. */
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u8 temp8;
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u16 temp16;
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@ -191,7 +191,7 @@ void rs780_nb_pci_table(device_t nb_dev)
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#endif
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}
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void rs780_nb_gfx_dev_table(device_t nb_dev, device_t dev)
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static void rs780_nb_gfx_dev_table(device_t nb_dev, device_t dev)
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{
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/* NB_InitGFXStraps */
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u32 MMIOBase, apc04, apc18, apc24;
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@ -214,27 +214,27 @@ void rs780_nb_gfx_dev_table(device_t nb_dev, device_t dev)
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pci_write_config8(dev, 0x04, 0x02);
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/* Program Straps. */
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strap = MMIOBase + 0x15020;
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strap = (volatile u32 *)(MMIOBase + 0x15020);
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#if (CONFIG_GFXUMA == 1)
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*strap = 1<<7; /* the format of BIF_MEM_AP_SIZE. 001->256MB? */
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#else
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*strap = 0; /* 128M SP memory, 000 -> 128MB */
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#endif
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strap = MMIOBase + 0x15000;
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strap = (volatile u32 *)(MMIOBase + 0x15000);
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*strap = 0x2c006300;
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strap = MMIOBase + 0x15010;
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strap = (volatile u32 *)(MMIOBase + 0x15010);
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*strap = 0x03015330;
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//strap = MMIOBase + 0x15020;
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//strap = (volatile u32 *)(MMIOBase + 0x15020);
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//*strap |= 0x00000040; /* Disable HDA device. */
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strap = MMIOBase + 0x15030;
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strap = (volatile u32 *)(MMIOBase + 0x15030);
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*strap = 0x00001002;
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strap = MMIOBase + 0x15040;
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strap = (volatile u32 *)(MMIOBase + 0x15040);
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*strap = 0x00000000;
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strap = MMIOBase + 0x15050;
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strap = (volatile u32 *)(MMIOBase + 0x15050);
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*strap = 0x00000000;
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strap = MMIOBase + 0x15220;
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strap = (volatile u32 *)(MMIOBase + 0x15220);
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*strap = 0x03c03800;
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strap = MMIOBase + 0x15060;
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strap = (volatile u32 *)(MMIOBase + 0x15060);
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*strap = 0x00000000;
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/* BIF switches into normal functional mode. */
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@ -252,8 +252,8 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port)
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u32 lc_state, reg, current_link_width, lane_mask;
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int8_t current, res = 0;
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u32 gfx_gpp_sb_sel;
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void set_pcie_dereset();
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void set_pcie_reset();
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void set_pcie_dereset(void);
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void set_pcie_reset(void);
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switch (port) {
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case 2 ... 3:
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@ -265,6 +265,9 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port)
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case 9 ... 10:
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gfx_gpp_sb_sel = PCIE_CORE_INDEX_GPP;
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break;
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default:
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gfx_gpp_sb_sel = -1;
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return 0;
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}
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while (count--) {
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@ -35,8 +35,8 @@
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#include <cpu/x86/msr.h>
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#include "rs780.h"
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void set_pcie_reset();
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void set_pcie_dereset();
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void set_pcie_reset(void);
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void set_pcie_dereset(void);
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#define CLK_CNTL_INDEX 0x8
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#define CLK_CNTL_DATA 0xC
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@ -89,7 +89,7 @@ typedef struct _MMIORANGE
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MMIORANGE MMIO[8], CreativeMMIO[8];
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MMIORANGE* AllocMMIO(MMIORANGE* pMMIO)
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static MMIORANGE* AllocMMIO(MMIORANGE* pMMIO)
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{
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int i;
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for (i=0; i<8; i++)
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@ -99,7 +99,7 @@ MMIORANGE* AllocMMIO(MMIORANGE* pMMIO)
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}
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return 0;
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}
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void FreeMMIO(MMIORANGE* pMMIO)
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static void FreeMMIO(MMIORANGE* pMMIO)
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{
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pMMIO->Base = 0;
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pMMIO->Limit = 0;
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@ -115,7 +115,7 @@ void FreeMMIO(MMIORANGE* pMMIO)
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#define MMIO_ATTRIB_BOTTOM_TO_TOP 1<<1
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#define MMIO_ATTRIB_SKIP_ZERO 1<<2
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u32 SetMMIO(u32 Base, u32 Limit, u8 Attribute, MMIORANGE *pMMIO)
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static u32 SetMMIO(u32 Base, u32 Limit, u8 Attribute, MMIORANGE *pMMIO)
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{
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int i;
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MMIORANGE * TempRange;
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@ -139,7 +139,7 @@ u32 SetMMIO(u32 Base, u32 Limit, u8 Attribute, MMIORANGE *pMMIO)
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return 0;
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}
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u8 FinalizeMMIO(MMIORANGE *pMMIO)
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static u8 FinalizeMMIO(MMIORANGE *pMMIO)
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{
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int i, j, n = 0;
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for(i=0; i<8; i++)
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@ -173,7 +173,7 @@ u8 FinalizeMMIO(MMIORANGE *pMMIO)
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return n;
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}
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CIM_STATUS GetCreativeMMIO(MMIORANGE *pMMIO)
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static CIM_STATUS GetCreativeMMIO(MMIORANGE *pMMIO)
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{
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CIM_STATUS Status = CIM_UNSUPPORTED;
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u8 Bus, Dev, Reg, BusStart, BusEnd;
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@ -241,11 +241,10 @@ CIM_STATUS GetCreativeMMIO(MMIORANGE *pMMIO)
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return Status;
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}
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void ProgramMMIO(MMIORANGE *pMMIO, u8 LinkID, u8 Attribute)
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static void ProgramMMIO(MMIORANGE *pMMIO, u8 LinkID, u8 Attribute)
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{
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int i, j, n = 7;
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device_t k8_f1;
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u32 temp32;
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k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1));
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@ -296,17 +295,15 @@ static void internal_gfx_pci_dev_init(struct device *dev)
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volatile u32 * pointer;
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int i;
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u16 command;
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u32 value, temp, Base32, Limit32;
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CIM_STATUS Status;
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u32 value;
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u16 deviceid, vendorid;
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device_t nb_dev = dev_find_slot(0, 0);
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device_t k8_f2 = dev_find_slot(0, PCI_DEVFN(0x18, 2));
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device_t k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1));
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device_t k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0));
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device_t dev0x14 = dev_find_slot(0, PCI_DEVFN(0x14, 4));
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struct southbridge_amd_rs780_config *cfg =
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(struct southbridge_amd_rs780_config *)dev->chip_info;
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/* We definetely will use this in future. Just leave it here. */
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/*struct southbridge_amd_rs780_config *cfg =
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(struct southbridge_amd_rs780_config *)dev->chip_info;*/
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deviceid = pci_read_config16(dev, PCI_DEVICE_ID);
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vendorid = pci_read_config16(dev, PCI_VENDOR_ID);
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@ -430,7 +427,8 @@ static void internal_gfx_pci_dev_init(struct device *dev)
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//vgainfo.ulSystemConfig |= 1<<1 | 1<<3 | 1<<4 | 1<<5 | 1<<6 | 1<<7 | 1;
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vgainfo.ulBootUpReqDisplayVector = 0; //?
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vgainfo.ulOtherDisplayMisc = 0; //?
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vgainfo.ulDDISlot1Config = 0x000c0011; //0; //?
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vgainfo.ulDDISlot1Config = 0x000c0011; //0; //VGA
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//vgainfo.ulDDISlot1Config = 0x000c00FF; //0; //HDMI
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vgainfo.ulDDISlot2Config = 0x00130022; //0; //?
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vgainfo.ucMemoryType = 2;
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/* UMA Channel Number: 1 or 2. */
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@ -978,7 +976,6 @@ static void dynamic_link_width_control(device_t nb_dev, device_t dev, u8 width)
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*/
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void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port)
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{
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u16 reg16;
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u32 reg32;
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struct southbridge_amd_rs780_config *cfg =
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(struct southbridge_amd_rs780_config *)nb_dev->chip_info;
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@ -989,20 +986,6 @@ void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port)
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/* GFX Core Initialization */
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//if (port == 2) return;
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/* step 1, lane reversal (only need if CMOS option is enabled) */
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if (cfg->gfx_lane_reversal) {
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set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 2, 1 << 2);
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if (cfg->gfx_dual_slot)
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set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 3, 1 << 3);
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}
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printk(BIOS_INFO, "rs780_gfx_init step1.\n");
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/* step 1.1, dual-slot gfx configuration (only need if CMOS option is enabled) */
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/* AMD calls the configuration CrossFire */
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if (cfg->gfx_dual_slot)
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set_nbmisc_enable_bits(nb_dev, 0x0, 0xf << 8, 5 << 8);
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printk(BIOS_INFO, "rs780_gfx_init step2.\n");
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/* step 2, TMDS, (only need if CMOS option is enabled) */
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if (cfg->gfx_tmds) {
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}
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@ -1182,9 +1165,35 @@ void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port)
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/* Single-port/Dual-port configureation. */
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switch (cfg->gfx_dual_slot) {
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case 0:
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/* step 1, lane reversal (only need if CMOS option is enabled) */
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if (cfg->gfx_lane_reversal) {
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set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 2, 1 << 2);
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}
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printk_info("rs780_gfx_init step1.\n");
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printk_info("rs780_gfx_init step2.\n");
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printk_info("device = %x\n", dev->path.pci.devfn >> 3);
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if((dev->path.pci.devfn >> 3) == 2)
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single_port_configuration(nb_dev, dev);
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else{
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set_nbmisc_enable_bits(nb_dev, 0xc, 0, 0x2 << 2); /* hide the GFX bridge. */
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printk_info("If dev3.., single port. Do nothing.\n");
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}
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break;
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case 1:
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/* step 1, lane reversal (only need if CMOS option is enabled) */
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if (cfg->gfx_lane_reversal) {
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set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 2, 1 << 2);
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set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 3, 1 << 3);
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}
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printk_info("rs780_gfx_init step1.\n");
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/* step 1.1, dual-slot gfx configuration (only need if CMOS option is enabled) */
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/* AMD calls the configuration CrossFire */
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set_nbmisc_enable_bits(nb_dev, 0x0, 0xf << 8, 5 << 8);
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printk_info("rs780_gfx_init step2.\n");
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printk_info("device = %x\n", dev->path.pci.devfn >> 3);
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dual_port_configuration(nb_dev, dev);
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break;
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default:
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@ -101,20 +101,6 @@ static void PciePowerOffGppPorts(device_t nb_dev, device_t dev, u32 port)
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}
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}
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static void pcie_init(struct device *dev)
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{
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/* Enable pci error detecting */
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u32 dword;
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printk(BIOS_DEBUG, "pcie_init in rs780_pcie.c\n");
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/* System error enable */
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dword = pci_read_config32(dev, 0x04);
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dword |= (1 << 8); /* System error enable */
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dword |= (1 << 30); /* Clear possible errors */
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pci_write_config32(dev, 0x04, dword);
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}
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/**********************************************************************
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**********************************************************************/
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static void switching_gppsb_configurations(device_t nb_dev, device_t sb_dev)
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@ -249,9 +235,6 @@ void disable_pcie_bar3(device_t nb_dev)
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*****************************************/
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void rs780_gpp_sb_init(device_t nb_dev, device_t dev, u32 port)
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{
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u8 reg8;
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u16 reg16;
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device_t sb_dev;
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u32 gfx_gpp_sb_sel;
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struct southbridge_amd_rs780_config *cfg =
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(struct southbridge_amd_rs780_config *)nb_dev->chip_info;
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@ -406,44 +389,3 @@ void config_gpp_core(device_t nb_dev, device_t sb_dev)
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switching_gpp_configurations(nb_dev, sb_dev);
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ValidatePortEn(nb_dev);
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}
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/*****************************************
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* Compliant with CIM_33's PCIEMiscClkProg
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*****************************************/
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void pcie_config_misc_clk(device_t nb_dev)
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{
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u32 reg;
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struct bus pbus; /* fake bus for dev0 fun1 */
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reg = pci_read_config32(nb_dev, 0x4c);
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reg |= 1 << 0;
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pci_write_config32(nb_dev, 0x4c, reg);
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if (AtiPcieCfg.Config & PCIE_GFX_CLK_GATING) {
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/* TXCLK Clock Gating */
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set_nbmisc_enable_bits(nb_dev, 0x07, 3 << 0, 3 << 0);
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set_nbmisc_enable_bits(nb_dev, 0x07, 1 << 22, 1 << 22);
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set_pcie_enable_bits(nb_dev, 0x11 | PCIE_CORE_INDEX_GFX, (3 << 6) | (~0xf), 3 << 6);
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/* LCLK Clock Gating */
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reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0x94);
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reg &= ~(1 << 16);
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pci_cf8_conf1.write32(&pbus, 0, 1, 0x94, reg);
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}
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if (AtiPcieCfg.Config & PCIE_GPP_CLK_GATING) {
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/* TXCLK Clock Gating */
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set_nbmisc_enable_bits(nb_dev, 0x07, 3 << 4, 3 << 4);
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set_nbmisc_enable_bits(nb_dev, 0x07, 1 << 22, 1 << 22);
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set_pcie_enable_bits(nb_dev, 0x11 | PCIE_CORE_INDEX_GPPSB, (3 << 6) | (~0xf), 3 << 6);
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/* LCLK Clock Gating */
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reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0x94);
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reg &= ~(1 << 24);
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pci_cf8_conf1.write32(&pbus, 0, 1, 0x94, reg);
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}
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reg = pci_read_config32(nb_dev, 0x4c);
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reg &= ~(1 << 0);
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pci_write_config32(nb_dev, 0x4c, reg);
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}
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