mb/prodrive/hermes: Add new mainboard port
This patch adds support for the Prodrive Hermes mainboard. Tested with CoffeeLakeFspBinPkg FSP 7.0.68.41. Untested: * CNVi * Intel Graphics Tested: * CPU Intel Xeon E2288G * CPU Intel Core i3-9100F * CPU Intel Core i7 9700KF * CPU Intel Core i7 9700E * CPU Intel Core i7 9700F * CPU Intel Core i5 9600K * CPU Intel Pentium Gold G5400 * PCIe Link Width x8 on Slot6 by changing PCIe mux * All four DDR4 slots in different configurations * USB2.0 HDR1 * USB2.0 HDR2 * USB3.0 HDR * Slot1 * Slot2 * Slot3 * Slot4 * Slot6 * M2.M NVMEe * Ethernet PHYs 0-4 * Aspeed BMC PCIe * Aspeed BMC USB * Aspeed Graphics init * USB3 backplane all working * I801 SMBUS Not Working: * Intel HDA Change-Id: Id7d051d3fa6823618691d5572087c9ae589c2862 Signed-off-by: Christian Walter <christian.walter@9elements.com> Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38303 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This commit is contained in:
Christian Walter
Philipp Deppenwiese
parent
b7cf7d36d7
commit
b646e28769
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@ -130,6 +130,10 @@ The boards in this section are not real mainboards, but emulators.
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- [PQ7-M107](portwell/pq7-m107.md)
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## Prodrive
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- [Hermes](prodrive/hermes.md)
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## Protectli
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- [FW2B / FW4B](protectli/fw2b_fw4b.md)
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@ -0,0 +1,54 @@
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# Hermes
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Hermes is a regular ATX board designed for workstation PCs.
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The board features:
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* 5 PCIe 16x Gen3 slots
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* 4 ECC capable DDR4 DIMMs
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* 5 dedicated Ethernet ports
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* 1 BMC Ethernet port
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* VGA
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* COM port
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* 2 COM port headers
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* 4 SATA ports,
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* NVMe M2 slot
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* CNVi M2 slot
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* 3 optional DisplayPort outputs
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* optional TPM2
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## Required proprietary blobs
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- [Intel FSP2.0]
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- Intel SPS
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## Flashing coreboot
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* The BIOS flash can be updated over the BMC, but the update file has a proprietary format
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* For development a dediprog compatible pinheader is present which allows to use an EM100
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## Known issues
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- MRC caching does not work on cold boot with Intel SPS (see [Intel FSP2.0])
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## Technology
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```eval_rst
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+------------------+--------------------------------------------------+
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| CPU | CoffeeLake + CoffeeLake R (Core + Xeon) |
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+------------------+--------------------------------------------------+
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| PCH | Intel C246 |
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+------------------+--------------------------------------------------+
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| Coprocessor | Intel SPS (server version of the ME) |
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+------------------+--------------------------------------------------+
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| Super I/O | none |
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+------------------+--------------------------------------------------+
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| BMC | Aspeed AST2500 |
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+------------------+--------------------------------------------------+
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```
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## Extra links
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[flashrom]: https://flashrom.org/Flashrom
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[flashing tutorial]: ../../../../flash_tutorial/ext_power.md
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[Intel FSP2.0]: ../../../../soc/intel/fsp/index.md
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[AST2500]: https://www.aspeedtech.com/products.php?fPath=20&rId=440
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@ -0,0 +1,16 @@
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if VENDOR_PRODRIVE
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choice
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prompt "Mainboard model"
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source "src/mainboard/prodrive/*/Kconfig.name"
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endchoice
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source "src/mainboard/prodrive/*/Kconfig"
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config MAINBOARD_VENDOR
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string
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default "Prodrive"
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endif # VENDOR_PRODRIVE
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@ -0,0 +1,2 @@
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config VENDOR_PRODRIVE
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bool "Prodrive"
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@ -0,0 +1,64 @@
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config BOARD_PRODRIVE_HERMES_BASEBOARD
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def_bool n
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select SOC_INTEL_COFFEELAKE
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select BOARD_ROMSIZE_KB_32768
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select GENERIC_SPD_BIN
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select HAVE_ACPI_TABLES
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select SOC_INTEL_CANNONLAKE_PCH_H
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select SUPERIO_ASPEED_COMMON_PRE_RAM
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select SUPERIO_ASPEED_AST2400
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select DRIVERS_ASPEED_AST_COMMON
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select DRIVERS_ASPEED_AST2050
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select SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS
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select INTEL_LPSS_UART_FOR_CONSOLE
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select MAINBOARD_HAS_TPM2
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select MAINBOARD_HAS_LPC_TPM
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select INTEL_GMA_HAVE_VBT
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select SOC_INTEL_COMMON_BLOCK_HDA_VERB
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select AZALIA_PLUGIN_SUPPORT
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select ONBOARD_VGA_IS_PRIMARY
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select DISABLE_ACPI_HIBERNATE
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if BOARD_PRODRIVE_HERMES_BASEBOARD
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config MAINBOARD_FAMILY
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string
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default "PRODRIVE_HERMES_SERIES"
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config MAINBOARD_PART_NUMBER
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string
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default "Hermes CFL"
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config MAINBOARD_DIR
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string
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default "prodrive/hermes"
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config VARIANT_DIR
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string
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default "baseboard" if BOARD_PRODRIVE_HERMES_BASEBOARD
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config MAX_CPUS
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int
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default 16
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config OVERRIDE_DEVICETREE
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string
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default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
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config DIMM_SPD_SIZE
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int
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default 512
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config CONSOLE_POST
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bool
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default y
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config POST_IO
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bool
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default n
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config CBFS_SIZE
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hex
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default 0x900000
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endif # BOARD_PRODRIVE_HERMES_BASEBOARD
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@ -0,0 +1,3 @@
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config BOARD_PRODRIVE_HERMES
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bool "Hermes"
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select BOARD_PRODRIVE_HERMES_BASEBOARD
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@ -0,0 +1,12 @@
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# SPDX-License-Identifier: GPL-2.0-or-later
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subdirs-y += variants/$(VARIANT_DIR)
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CPPFLAGS_common += -I$(src)/mainboard/prodrive/hermes/variants/$(VARIANT_DIR)/include
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bootblock-y += bootblock.c
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romstage-y += memory.c
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romstage-y += eeprom.c
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ramstage-y += ramstage.c
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ramstage-y += mainboard.c
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ramstage-y += eeprom.c
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@ -0,0 +1,7 @@
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Category: server
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Vendor name: Prodrive
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ROM package: SOIC-8
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ROM protocol: SPI
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ROM socketed: n
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Flashrom support: y
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Release year: 2020
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@ -0,0 +1,33 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <bootblock_common.h>
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#include <console/console.h>
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#include <soc/gpio.h>
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#include <variant/gpio.h>
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#include "gpio.h"
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static void early_config_gpio(void)
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{
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/* This is a hack for FSP because it does things in MemoryInit()
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* which it shouldn't do. We have to prepare certain gpios here
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* because of the brokenness in FSP. */
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size_t num = 0;
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const struct pad_config *early_gpio_table = get_early_gpio_table(&num);
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gpio_configure_pads(early_gpio_table, num);
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}
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void bootblock_mainboard_early_init(void)
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{
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early_config_gpio();
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}
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void bootblock_mainboard_init(void)
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{
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u8 bmc_hsi = (gpio_get(GPP_K13) << 3) |
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(gpio_get(GPP_K12) << 2) |
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(gpio_get(GPP_K14) << 1) |
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(gpio_get(GPP_K16) << 0);
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printk(BIOS_INFO, "BMC HSI 0x%x\n", bmc_hsi);
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}
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@ -0,0 +1,48 @@
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chip soc/intel/cannonlake
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register "common_soc_config.chipset_lockdown" = CHIPSET_LOCKDOWN_COREBOOT
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device domain 0 on
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device pci 00.0 on end # Host Bridge
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device pci 01.0 on # PEG x8 / Slot 2
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smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT2" "SlotDataBusWidth8X"
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end
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device pci 01.1 on # PEG x4 or x8 / Slot 6
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smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT6" "SlotDataBusWidth4X"
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end
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device pci 01.2 on # PEG x4 or disabled / Slot 4
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smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT4" "SlotDataBusWidth4X"
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end
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device pci 04.0 on end # SA Thermal device
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device pci 04.0 on end # Intel Xeon E3
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device pci 08.0 on end # Gaussian Mixture
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device pci 12.0 on end # Thermal Subsystem
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device pci 14.0 on end # USB xHCI
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device pci 14.1 on end # USB xDCI (OTG)
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device pci 14.2 on end # RAM controller
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device pci 14.5 off end # SDCard
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device pci 16.0 on end # Management Engine Interface
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device pci 16.1 on end # Management Engine Interface
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device pci 16.4 on end # Management Engine Interface
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device pci 17.0 on end # SATA
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device pci 1d.6 on
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device pci 00.0 on # Aspeed PCI Bridge
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device pci 00.0 on end # Aspeed 2500 VGA
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end
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end # PCIe
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device pci 1f.0 on # LPC Interface
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chip drivers/pc80/tpm
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device pnp 0c31.0 on end
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end
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# AST2500, but not enabled to decode LPC cycles
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end
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device pci 1f.3 on end
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device pci 1f.4 on end # SMBus
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device pci 1f.5 on end # PCH SPI
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end
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end
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@ -0,0 +1,27 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <acpi/acpi.h>
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DefinitionBlock(
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"dsdt.aml",
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"DSDT",
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0x02, // DSDT revision: ACPI v2.0 and up
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OEM_ID,
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ACPI_TABLE_CREATOR,
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0x20110725 // OEM revision
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)
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{
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#include <soc/intel/cannonlake/acpi/platform.asl>
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// global NVS and variables
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#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
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Scope (\_SB) {
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Device (PCI0) {
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#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
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#include <soc/intel/cannonlake/acpi/southbridge.asl>
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}
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}
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#include <southbridge/intel/common/acpi/sleepstates.asl>
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}
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@ -0,0 +1,67 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <device/pci_ops.h>
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#include <console/console.h>
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#include <device/smbus_host.h>
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#include "variants/baseboard/include/eeprom.h"
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/*
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* Check Signature in EEPROM (M24C32-FMN6TP)
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* If signature is there we assume that that the content is valid
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*/
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int check_signature(u8 addr)
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{
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u8 blob[8] = {0};
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if (!read_write_config(addr, blob, EEPROM_OFFSET_FSP_SIGNATURE, 0, ARRAY_SIZE(blob))) {
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// Check Signature
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if (*(uint64_t *)blob == FSP_UPD_SIGNATURE) {
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printk(BIOS_DEBUG, "CFG EEPROM: Signature valid.\n");
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return 1;
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}
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printk(BIOS_DEBUG, "CFG EEPROM: Signature invalid - skipping option write.\n");
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return 0;
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}
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return 0;
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}
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// Read data from offset and write it to offset in UPD
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bool read_write_config(u8 addr, void *blob, size_t read_offset, size_t write_offset,
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size_t size)
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{
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int ret = 0;
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#if ENV_ROMSTAGE
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pci_devfn_t dev = PCI_DEV(0, PCH_DEV_SLOT_LPC, 4);
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#else
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const struct device *dev = pcidev_on_root(PCH_DEV_SLOT_LPC, 4);
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#endif
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u32 smb_ctrl_reg = pci_read_config32(dev, HOSTC);
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pci_write_config32(dev, HOSTC, smb_ctrl_reg | HOSTC_I2C_EN);
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printk(BIOS_SPEW, "%s\tOffset: %04zx\tSize: %02zx\n", __func__,
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read_offset, size);
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/* We can always read two bytes at a time */
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for (size_t i = 0; i < size; i = i + 2) {
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u8 tmp[2] = {0};
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ret = do_smbus_process_call(SMBUS_IO_BASE, addr, 0,
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swab16(read_offset + i), (uint16_t *)&tmp[0]);
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if (ret < 0)
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break;
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// Write to UPD
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uint8_t *writePointer = (uint8_t *)blob + write_offset + i;
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if (size > 1 && (size % 2 == 0))
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memcpy(writePointer, tmp, 2);
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else
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*writePointer = tmp[0];
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}
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/* Restore I2C_EN bit */
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pci_write_config32(dev, HOSTC, smb_ctrl_reg);
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return ret;
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}
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@ -0,0 +1,170 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <device/azalia_device.h>
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const u32 cim_verb_data[] = {
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0x10ec0888, /* Codec Vendor / Device ID: Realtek ALC888 */
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0x10ec0888, /* Subsystem ID */
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10, /* Number of 4 dword sets */
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AZALIA_SUBVENDOR(0, 0x10ec0888),
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/* Port A: Front, Audio Header #1 */
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AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_DESC(
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INTEGRATED,
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INTERNAL,
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SPECIAL7,
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LINE_OUT,
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OTHER_ANALOG,
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COLOR_UNKNOWN,
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false,
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0xf,
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0
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)),
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/* Port B: Mic1, Line input (pink) */
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AZALIA_PIN_CFG(0, 0x15, AZALIA_PIN_DESC(
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JACK,
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EXTERNAL_PRIMARY_CHASSIS,
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REAR, //FIXME
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LINE_IN,
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STEREO_MONO_1_8,
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PINK,
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false,
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0xf,
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0
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)),
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/* Port C: Line, Speaker (only L) */
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AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_DESC(
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INTEGRATED,
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INTERNAL,
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NA,
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SPEAKER,
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TYPE_UNKNOWN,
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COLOR_UNKNOWN,
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false,
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0xf,
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0
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)),
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/* Port D: Sidesurr, Line out (green) */
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AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_DESC(
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//JACK,
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LINE_OUT,
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EXTERNAL_PRIMARY_CHASSIS,
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REAR, //FIXME
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LINE_OUT,
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STEREO_MONO_1_8,
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GREEN,
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false,
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0xf,
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0
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)),
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/* Port E: Line2, Line input (blue) */
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AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_DESC(
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JACK,
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EXTERNAL_PRIMARY_CHASSIS,
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REAR, //FIXME
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LINE_IN,
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STEREO_MONO_1_8,
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BLUE,
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false,
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0xf,
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0
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)),
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/* Port F: Mic2, Audio Header #2 */
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AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_DESC(
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INTEGRATED,
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INTERNAL,
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SPECIAL7,
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LINE_IN,
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OTHER_ANALOG,
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COLOR_UNKNOWN,
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false,
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0xf,
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0
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)),
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/* Port G: Not connected */
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AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_DESC(
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NC,
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LOCATION_OTHER,
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NA,
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DEVICE_OTHER,
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TYPE_OTHER,
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COLOR_OTHER,
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true,
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0,
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0
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)),
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/* Port H: Not connected */
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AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_DESC(
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NC,
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LOCATION_OTHER,
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NA,
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DEVICE_OTHER,
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TYPE_OTHER,
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COLOR_OTHER,
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true,
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0,
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0
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)),
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/* S/PDIF-OUT */
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AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_DESC(
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||||
INTEGRATED,
|
||||
INTERNAL,
|
||||
NA,
|
||||
SPDIF_OUT,
|
||||
OTHER_DIGITAL,
|
||||
COLOR_UNKNOWN,
|
||||
true,
|
||||
0xf,
|
||||
0
|
||||
)),
|
||||
/* S/PDIF-IN */
|
||||
AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_DESC(
|
||||
INTEGRATED,
|
||||
INTERNAL,
|
||||
NA,
|
||||
SPDIF_IN,
|
||||
OTHER_DIGITAL,
|
||||
COLOR_UNKNOWN,
|
||||
true,
|
||||
0xf,
|
||||
0
|
||||
)),
|
||||
|
||||
//FIXME COdec ID
|
||||
/*
|
||||
* VerbTable: CFL Display Audio Codec
|
||||
* Revision ID = 0xFF
|
||||
* Codec Vendor: 0x8086280B
|
||||
*/
|
||||
|
||||
0x8086280B,
|
||||
0xFFFFFFFF,
|
||||
5, /* Number of 4 dword sets */
|
||||
|
||||
/*
|
||||
* Display Audio Verb Table
|
||||
* For GEN9, the Vendor Node ID is 08h
|
||||
* Port to be exposed to the inbox driver in the vanilla mode
|
||||
* PORT C - BIT[7:6] = 01b
|
||||
*/
|
||||
0x00878140,
|
||||
0x00878140,
|
||||
0x00878140,
|
||||
0x00878140,
|
||||
/* Pin Widget 5 - PORT B - Configuration Default: 0x18560010 */
|
||||
AZALIA_PIN_CFG(2, 0x05, 0x18560010),
|
||||
/* Pin Widget 6 - PORT C - Configuration Default: 0x18560020 */
|
||||
AZALIA_PIN_CFG(2, 0x06, 0x18560020),
|
||||
/* Pin Widget 7 - PORT D - Configuration Default: 0x18560030 */
|
||||
AZALIA_PIN_CFG(2, 0x07, 0x18560030),
|
||||
/* Disable the third converter and third Pin (NID 08h) */
|
||||
0x00878140,
|
||||
0x00878140,
|
||||
0x00878140,
|
||||
0x00878140,
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[0] = {};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
|
|
@ -0,0 +1,89 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/device.h>
|
||||
#include "gpio.h"
|
||||
|
||||
/* FIXME: Example code below */
|
||||
|
||||
static void mb_configure_dp1_pwr(bool enable)
|
||||
{
|
||||
gpio_output(GPP_K3, enable);
|
||||
}
|
||||
|
||||
static void mb_configure_dp2_pwr(bool enable)
|
||||
{
|
||||
gpio_output(GPP_K4, enable);
|
||||
}
|
||||
|
||||
static void mb_configure_dp3_pwr(bool enable)
|
||||
{
|
||||
gpio_output(GPP_K5, enable);
|
||||
}
|
||||
|
||||
static void mb_pcie_reset_pch_slots(bool enable)
|
||||
{
|
||||
gpio_output(GPP_K0, enable);
|
||||
}
|
||||
|
||||
static void mb_pcie_reset_cpu_slots(bool enable)
|
||||
{
|
||||
gpio_output(GPP_K1, enable);
|
||||
}
|
||||
|
||||
static void mb_pcie_reset_cnvi_slot(bool enable)
|
||||
{
|
||||
gpio_output(GPP_K2, enable);
|
||||
}
|
||||
|
||||
static void mb_hda_amp_enable(bool enable)
|
||||
{
|
||||
gpio_output(GPP_C19, enable);
|
||||
}
|
||||
|
||||
static void mb_usb31_rp1_pwr_enable(bool enable)
|
||||
{
|
||||
gpio_output(GPP_G0, enable);
|
||||
}
|
||||
|
||||
static void mb_usb31_rp2_pwr_enable(bool enable)
|
||||
{
|
||||
gpio_output(GPP_G1, enable);
|
||||
}
|
||||
|
||||
static void mb_usb31_fp_pwr_enable(bool enable)
|
||||
{
|
||||
gpio_output(GPP_G2, enable);
|
||||
}
|
||||
|
||||
static void mb_usb2_fp1_pwr_enable(bool enable)
|
||||
{
|
||||
gpio_output(GPP_G3, enable);
|
||||
}
|
||||
|
||||
static void mb_usb2_fp2_pwr_enable(bool enable)
|
||||
{
|
||||
gpio_output(GPP_G4, enable);
|
||||
}
|
||||
|
||||
static void mainboard_enable(struct device *dev)
|
||||
{
|
||||
/* FIXME: Do runtime configuration once the board is production ready */
|
||||
mb_configure_dp1_pwr(1);
|
||||
mb_configure_dp2_pwr(1);
|
||||
mb_configure_dp3_pwr(1);
|
||||
if (0) {
|
||||
mb_pcie_reset_pch_slots(1);
|
||||
mb_pcie_reset_cpu_slots(0);
|
||||
mb_pcie_reset_cnvi_slot(0);
|
||||
}
|
||||
mb_hda_amp_enable(1);
|
||||
mb_usb31_rp1_pwr_enable(1);
|
||||
mb_usb31_rp2_pwr_enable(1);
|
||||
mb_usb31_fp_pwr_enable(1);
|
||||
mb_usb2_fp1_pwr_enable(1);
|
||||
mb_usb2_fp2_pwr_enable(1);
|
||||
}
|
||||
|
||||
struct chip_operations mainboard_ops = {
|
||||
.enable_dev = mainboard_enable,
|
||||
};
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <variant/variants.h>
|
||||
#include <soc/cnl_memcfg_init.h>
|
||||
|
||||
static const struct cnl_mb_cfg baseboard_memcfg_cfg = {
|
||||
/* Access memory info through SMBUS. */
|
||||
.spd[0] = {
|
||||
.read_type = READ_SMBUS,
|
||||
.spd_spec = {.spd_smbus_address = 0xA0}
|
||||
},
|
||||
.spd[1] = {
|
||||
.read_type = READ_SMBUS,
|
||||
.spd_spec = {.spd_smbus_address = 0xA2}
|
||||
},
|
||||
.spd[2] = {
|
||||
.read_type = READ_SMBUS,
|
||||
.spd_spec = {.spd_smbus_address = 0xA4}
|
||||
},
|
||||
.spd[3] = {
|
||||
.read_type = READ_SMBUS,
|
||||
.spd_spec = {.spd_smbus_address = 0xA6}
|
||||
},
|
||||
|
||||
/* Baseboard uses 121, 81 and 100 rcomp resistors */
|
||||
.rcomp_resistor = {121, 81, 100},
|
||||
|
||||
/* Baseboard Rcomp target values. */
|
||||
.rcomp_targets = {100, 40, 20, 20, 26},
|
||||
|
||||
/* Baseboard is an interleaved design */
|
||||
.dq_pins_interleaved = 1,
|
||||
|
||||
/* Baseboard is using config 2 for vref_ca */
|
||||
.vref_ca_config = 2,
|
||||
|
||||
/* Disable Early Command Training */
|
||||
.ect = 0,
|
||||
};
|
||||
|
||||
const struct cnl_mb_cfg *variant_memcfg_config(void)
|
||||
{
|
||||
return &baseboard_memcfg_cfg;
|
||||
}
|
||||
|
|
@ -0,0 +1,34 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <soc/ramstage.h>
|
||||
#include <variant/gpio.h>
|
||||
#include "variants/baseboard/include/eeprom.h"
|
||||
|
||||
static fsp_params parmas_list[] = {
|
||||
// FIXME: Fill with additional options
|
||||
};
|
||||
|
||||
void mainboard_silicon_init_params(FSP_S_CONFIG *params)
|
||||
{
|
||||
size_t num = 0;
|
||||
const struct pad_config *gpio_table = get_gpio_table(&num);
|
||||
|
||||
/* Configure pads prior to SiliconInit() in case there's any
|
||||
dependencies during hardware initialization. */
|
||||
gpio_configure_pads(gpio_table, num);
|
||||
|
||||
params->SataLedEnable = 1;
|
||||
|
||||
// Overwrite params
|
||||
if (!check_signature(I2C_ADDR_EEPROM))
|
||||
return;
|
||||
|
||||
for (u8 i = 0; i <= ARRAY_SIZE(parmas_list); i++) {
|
||||
if (ARRAY_SIZE(parmas_list) == 0)
|
||||
break;
|
||||
read_write_config(I2C_ADDR_EEPROM, params, EEPROM_OFFSET_FSP_CONFIG +
|
||||
parmas_list[i].offset,
|
||||
EEPROM_OFFSET_FSP_CONFIG + parmas_list[i].offset,
|
||||
parmas_list[i].size);
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <soc/cnl_memcfg_init.h>
|
||||
#include <soc/romstage.h>
|
||||
#include <variant/variants.h>
|
||||
#include "variants/baseboard/include/eeprom.h"
|
||||
|
||||
static fsp_params parmas_list[] = {
|
||||
GET_VALUE(RMT),
|
||||
GET_VALUE(HyperThreading),
|
||||
GET_VALUE(BootFrequency)
|
||||
};
|
||||
|
||||
void mainboard_memory_init_params(FSPM_UPD *memupd)
|
||||
{
|
||||
memupd->FspmConfig.UserBd = 7;
|
||||
memupd->FspmTestConfig.SmbusSpdWriteDisable = 0;
|
||||
memupd->FspmConfig.IedSize = 0x400000;
|
||||
cannonlake_memcfg_init(&memupd->FspmConfig, variant_memcfg_config());
|
||||
|
||||
// Overwrite memupd
|
||||
if (!check_signature(I2C_ADDR_EEPROM))
|
||||
return;
|
||||
|
||||
for (size_t i = 0; i < ARRAY_SIZE(parmas_list); i++) {
|
||||
read_write_config(I2C_ADDR_EEPROM, memupd, EEPROM_OFFSET_FSP_CONFIG +
|
||||
parmas_list[i].offset,
|
||||
EEPROM_OFFSET_FSP_CONFIG + parmas_list[i].offset,
|
||||
parmas_list[i].size);
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
## SPDX-License-Identifier: GPL-2.0-or-later
|
||||
|
||||
bootblock-y += gpio.c
|
||||
ramstage-y += gpio.c
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
Category: server
|
||||
Vendor name: Prodrive
|
||||
Board name: Hermes
|
||||
Board URL: TBD
|
||||
ROM protocol: SPI
|
||||
ROM socketed: n
|
||||
Flashrom support: y
|
||||
Binary file not shown.
|
|
@ -0,0 +1,402 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include "include/variant/gpio.h"
|
||||
#include <commonlib/helpers.h>
|
||||
|
||||
/* Pad configuration in ramstage */
|
||||
static const struct pad_config gpio_table[] = {
|
||||
/* ------- GPIO Group GPP_A ------- */
|
||||
|
||||
/* ISH */
|
||||
PAD_NC(GPP_A17, NONE),
|
||||
PAD_NC(GPP_A18, NONE),
|
||||
PAD_NC(GPP_A19, NONE),
|
||||
PAD_NC(GPP_A20, NONE),
|
||||
PAD_NC(GPP_A21, NONE),
|
||||
PAD_NC(GPP_A22, NONE),
|
||||
PAD_NC(GPP_A23, NONE),
|
||||
|
||||
/* ------- GPIO Group GPP_B ------- */
|
||||
PAD_NC(GPP_B0, NONE),
|
||||
PAD_NC(GPP_B1, NONE),
|
||||
|
||||
/* GPP_B2 - M2_E_BT_UART_WAKE_n */
|
||||
PAD_CFG_GPI_INT(GPP_B2, NONE, DEEP, OFF),
|
||||
|
||||
/* GPP_B3 - PCH_M2_E_BT_KILL_n : handled at runtime */
|
||||
/* GPP_B4 - PCH_M2_E_WLAN_KILL_n : handled at runtime */
|
||||
|
||||
/* SRCCLKREQ0# - SRCCLKREQ5# */
|
||||
PAD_NC(GPP_B5, NONE),
|
||||
PAD_NC(GPP_B6, NONE),
|
||||
PAD_NC(GPP_B7, NONE),
|
||||
PAD_NC(GPP_B8, NONE),
|
||||
PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), /* M2_M_CLK_REQ_n */
|
||||
PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), /* M2_E_CLK_REQ_n */
|
||||
|
||||
PAD_NC(GPP_B11, NONE),
|
||||
|
||||
/* GPP_B12 - SLP_S0_n */
|
||||
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
|
||||
/* GPP_B13 - PLTRST_n */
|
||||
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
|
||||
|
||||
/* GPP_B14 - SPKR */
|
||||
PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
|
||||
|
||||
/* GSPI0 */
|
||||
PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* SPI0_CS */
|
||||
PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), /* SPI0_CLK */
|
||||
PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* SPI0_MISO */
|
||||
PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), /* SPI0_MOSI */
|
||||
|
||||
/* GSPI1 */
|
||||
PAD_NC(GPP_B19, NONE),
|
||||
PAD_NC(GPP_B20, NONE),
|
||||
PAD_NC(GPP_B21, NONE),
|
||||
PAD_NC(GPP_B22, NONE),
|
||||
|
||||
PAD_CFG_NF(GPP_B23, NONE, DEEP, NF1), /* PCH_SML1_ALERT_n */
|
||||
|
||||
/* ------- GPIO Group GPP_C ------- */
|
||||
/* SML0 - Used by CSME */
|
||||
PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* PCH_SML0_CLK */
|
||||
PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* PCH_SML0_DATA */
|
||||
PAD_CFG_NF(GPP_C5, NONE, DEEP, NF1), /* PCH_SML0_ALERT_N */
|
||||
|
||||
/* SML1 - Used by CSME */
|
||||
PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), /* PCH_SML1_CLK */
|
||||
PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* PCH_SML1_DATA */
|
||||
|
||||
/* UART0 */
|
||||
PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0_RXD */
|
||||
PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* UART0_TXD */
|
||||
PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1), /* UART0_RTS_N */
|
||||
PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), /* UART0_CTS_N */
|
||||
|
||||
/* UART1 */
|
||||
PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), /* UART1_RXD */
|
||||
PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), /* UART1_TXD */
|
||||
PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1), /* UART1_RTS_N */
|
||||
PAD_CFG_NF(GPP_C15, NONE, DEEP, NF1), /* UART1_CTS_N */
|
||||
|
||||
PAD_NC(GPP_C17, NONE),
|
||||
|
||||
PAD_CFG_GPI_INT(GPP_C18, NONE, PLTRST, OFF), /* AUD_FPA_PRSNT_n */
|
||||
/* GPP_C19 - AUD_AMP_EN : configured at runtime */
|
||||
|
||||
/* UART2 */
|
||||
PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* UART2_RXD */
|
||||
PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* UART2_TXD */
|
||||
PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1), /* UART2_RTS_N */
|
||||
PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), /* UART2_CTS_N */
|
||||
|
||||
/* ------- GPIO Group GPP_D ------- */
|
||||
/* SPI1 */
|
||||
PAD_NC(GPP_D0, NONE),
|
||||
PAD_NC(GPP_D1, NONE),
|
||||
PAD_NC(GPP_D2, NONE),
|
||||
PAD_NC(GPP_D3, NONE),
|
||||
|
||||
PAD_NC(GPP_D4, NONE),
|
||||
|
||||
/* I2S2 */
|
||||
PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), /* M2_E_BT_PCMFRM_CRF_RST_n */
|
||||
PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), /* M2_E_BT_PCMOUT_CLKREQ0 */
|
||||
PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), /* M2_E_BT_PCMIN */
|
||||
PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), /* M2_E_BT_PCMCLK */
|
||||
|
||||
/* ISH SPI */
|
||||
PAD_NC(GPP_D9, NONE),
|
||||
PAD_NC(GPP_D10, NONE),
|
||||
PAD_NC(GPP_D11, NONE),
|
||||
PAD_NC(GPP_D12, NONE),
|
||||
|
||||
/* ISH UART */
|
||||
PAD_NC(GPP_D13, NONE),
|
||||
PAD_NC(GPP_D14, NONE),
|
||||
PAD_NC(GPP_D15, NONE),
|
||||
PAD_NC(GPP_D16, NONE),
|
||||
|
||||
/* DMIC */
|
||||
PAD_NC(GPP_D17, NONE),
|
||||
PAD_NC(GPP_D18, NONE),
|
||||
PAD_NC(GPP_D19, NONE),
|
||||
PAD_NC(GPP_D20, NONE),
|
||||
|
||||
PAD_NC(GPP_D21, NONE),
|
||||
PAD_NC(GPP_D22, NONE),
|
||||
PAD_NC(GPP_D23, NONE),
|
||||
|
||||
/* ------- GPIO Group GPP_G ------- */
|
||||
/* GPP_G0 - USB31_RP1_PWR_EN : configured at runtime */
|
||||
/* GPP_G1 - USB31_RP2_PWR_EN : configured at runtime */
|
||||
/* GPP_G2 - USB31_FP_PWR_EN : configured at runtime */
|
||||
/* GPP_G3 - USB2_FP1_PWR_EN : configured at runtime */
|
||||
/* GPP_G4 - USB2_FP2_PWR_EN : configured at runtime */
|
||||
|
||||
PAD_NC(GPP_G5, NONE),
|
||||
PAD_NC(GPP_G6, NONE),
|
||||
PAD_NC(GPP_G7, NONE),
|
||||
|
||||
/* ------- GPIO Group GPD ------- */
|
||||
/* GPD0 - BATLOW */
|
||||
PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
|
||||
/* GPD1 - ACPRESENT */
|
||||
PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
|
||||
/* GPD2 - LAN_WAKE# */
|
||||
PAD_CFG_NF(GPD2, NONE, DEEP, NF1),
|
||||
/* GPD3 - PRWBTN# */
|
||||
PAD_CFG_NF(GPD3, NONE, DEEP, NF1),
|
||||
/* GPD4 - SLP_S3# */
|
||||
PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
|
||||
/* GPD5 - SLP_S4# */
|
||||
PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
|
||||
/* GPD6 - SLP_A# */
|
||||
PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
|
||||
/* GPD7 - GPIO */
|
||||
PAD_NC(GPD7, NONE),
|
||||
/* GPD8 - SUSCLK */
|
||||
PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
|
||||
/* GPD9 - SLP_WLAN */
|
||||
PAD_CFG_NF(GPD9, NONE, DEEP, NF1),
|
||||
/* GPD10 - SLP_S5# */
|
||||
PAD_CFG_NF(GPD10, NONE, DEEP, NF1),
|
||||
/* GPD11 - LAN_DISABLE_n */
|
||||
PAD_CFG_NF(GPD11, NONE, DEEP, NF1),
|
||||
|
||||
/* ------- GPIO Group GPP_K ------- */
|
||||
/* GPP_K0 - PERST_PCH_SLOTS_n : configured at runtime */
|
||||
/* GPP_K1 - PERST_CPU_SLOTS_n : configured at runtime */
|
||||
/* GPP_K2 - PERST_CNVI_SLOTS_n : configured at runtime */
|
||||
/* GPP_K3 - DP1_PWR_EN : configured at runtime */
|
||||
/* GPP_K4 - DP2_PWR_EN : configured at runtime */
|
||||
/* GPP_K5 - DP3_PWR_EN : configured at runtime */
|
||||
|
||||
PAD_NC(GPP_K6, NONE),
|
||||
|
||||
/* GPP_K7 - EN_3V3_KEYM_PCH : configured at runtime */
|
||||
|
||||
PAD_NC(GPP_K8, NONE),
|
||||
PAD_NC(GPP_K9, NONE),
|
||||
PAD_NC(GPP_K10, NONE),
|
||||
PAD_NC(GPP_K11, NONE),
|
||||
|
||||
/* K12 - K16 in early GPIO config */
|
||||
|
||||
PAD_NC(GPP_K17, NONE),
|
||||
|
||||
/* GPP_K18/!NMI - NC */
|
||||
PAD_NC(GPP_K18, NONE),
|
||||
/* GPP_K19/!SMI - NC */
|
||||
PAD_NC(GPP_K19, NONE),
|
||||
|
||||
/* GPP_K20 - CPU_CATERR_PCH_n */
|
||||
PAD_CFG_GPI(GPP_K20, NONE, DEEP),
|
||||
/* GPP_K21 - TPM_INT_n */
|
||||
PAD_CFG_GPI_INT(GPP_K21, NONE, DEEP, OFF), // Trigger?
|
||||
/* GPP_K22 - NC */
|
||||
PAD_NC(GPP_K22, NONE),
|
||||
/* GPP_K23 - NC */
|
||||
PAD_NC(GPP_K23, NONE),
|
||||
|
||||
/* ------- GPIO Group GPP_H ------- */
|
||||
|
||||
/* SRCCLKREQ6# - SRCCLKREQ10# not used as CLKREQ, external 10K pullup */
|
||||
PAD_CFG_GPI(GPP_H0, NONE, DEEP), /* PCIE_SLOT1_PRSNT_PCH_n */
|
||||
PAD_CFG_GPI(GPP_H1, NONE, DEEP), /* PCIE_SLOT2_PRSNT_PCH_n */
|
||||
PAD_CFG_GPI(GPP_H2, NONE, DEEP), /* PCIE_SLOT3_PRSNT_PCH_n */
|
||||
PAD_CFG_GPI(GPP_H3, NONE, DEEP), /* PCIE_SLOT4_PRSNT_PCH_n */
|
||||
PAD_CFG_GPI(GPP_H4, NONE, DEEP), /* PCIE_SLOT6_PRSNT_PCH_n */
|
||||
|
||||
PAD_CFG_GPI(GPP_H4, NONE, DEEP), /* PCIE_SLOT6_PRSNT_PCH_n */
|
||||
|
||||
/* GPP_H5 - PCH_HBLED_n configured in early init */
|
||||
|
||||
/* SRCCLKREQ13# - SRCCLKREQ15# */
|
||||
PAD_NC(GPP_H7, NONE),
|
||||
PAD_NC(GPP_H8, NONE),
|
||||
PAD_NC(GPP_H9, NONE),
|
||||
|
||||
/* SML2 - Used by CSME */
|
||||
PAD_NC(GPP_H10, NONE),
|
||||
PAD_NC(GPP_H11, NONE),
|
||||
PAD_NC(GPP_H12, NONE),
|
||||
|
||||
/* SML3 - Used by CSME */
|
||||
PAD_NC(GPP_H13, NONE),
|
||||
PAD_NC(GPP_H14, NONE),
|
||||
PAD_NC(GPP_H15, NONE),
|
||||
|
||||
/* SML4 - Used by CSME */
|
||||
PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), /* PCIE_SMB_CLK */
|
||||
PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), /* PCIE_SMB_DATA */
|
||||
PAD_NC(GPP_H18, NONE),
|
||||
|
||||
/* ISH I2C0 */
|
||||
PAD_NC(GPP_H19, NONE),
|
||||
PAD_NC(GPP_H20, NONE),
|
||||
|
||||
/* ISH I2C1 */
|
||||
PAD_NC(GPP_H21, NONE),
|
||||
PAD_NC(GPP_H22, NONE),
|
||||
|
||||
PAD_NC(GPP_H23, NONE),
|
||||
|
||||
/* ------- GPIO Group GPP_E ------- */
|
||||
/* GPP_E0 - NC */
|
||||
PAD_NC(GPP_E0, NONE),
|
||||
/* GPP_E1 - M2_SATA_PCIE_SEL */
|
||||
PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1),
|
||||
/* GPP_E2 - NC */
|
||||
PAD_NC(GPP_E2, NONE),
|
||||
/* GPP_E3 - NC */
|
||||
PAD_NC(GPP_E3, NONE),
|
||||
/* GPP_E4 - NC */
|
||||
PAD_NC(GPP_E4, NONE),
|
||||
|
||||
/* GPP_E5 - PCH_M2_SATA_DEVSLP1 */
|
||||
PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1),
|
||||
/* GPP_E6 - NC */
|
||||
PAD_NC(GPP_E6, NONE),
|
||||
/* GPP_E8 - SATALED# */
|
||||
PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
|
||||
|
||||
/* GPP_E9 - USB31_RP1_OC_N */
|
||||
PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
|
||||
/* GPP_E10 - USB31_RP2_OC_N */
|
||||
PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),
|
||||
/* GPP_E11 - USB31_FP_OC_N */
|
||||
PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),
|
||||
/* GPP_E12 - USB2_FP1_OC_N */
|
||||
PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1),
|
||||
|
||||
/* ------- GPIO Group GPP_F ------- */
|
||||
/* SATAGP3-7 */
|
||||
PAD_NC(GPP_F0, NONE),
|
||||
PAD_NC(GPP_F1, NONE),
|
||||
PAD_NC(GPP_F2, NONE),
|
||||
PAD_NC(GPP_F3, NONE),
|
||||
PAD_NC(GPP_F4, NONE),
|
||||
|
||||
/* SATA DEVSLP3-7 */
|
||||
PAD_NC(GPP_F5, NONE),
|
||||
PAD_NC(GPP_F6, NONE),
|
||||
PAD_NC(GPP_F7, NONE),
|
||||
PAD_NC(GPP_F8, NONE),
|
||||
PAD_NC(GPP_F9, NONE),
|
||||
|
||||
/* SGPIO has external 2K pullups */
|
||||
/* GPP_F10 - SATA_SCLOCK */
|
||||
PAD_CFG_NF(GPP_F10, NONE, DEEP, NF1),
|
||||
/* GPP_F11 - SATA_SLOAD */
|
||||
PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1),
|
||||
/* GPP_F12 - SATA_SDATAOUT1 */
|
||||
PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
|
||||
/* GPP_F13 - SATA_BMC_SDATAOUT0 */
|
||||
PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),
|
||||
|
||||
/* GPP_F14 - PS_ON_PCH_n */
|
||||
PAD_CFG_NF(GPP_F14, NONE, DEEP, NF2),
|
||||
/* GPP_F15 - USB2_FP2_OC_N */
|
||||
PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),
|
||||
|
||||
/* GPP_F16 - NC/PU */
|
||||
PAD_NC(GPP_F16, NONE),
|
||||
/* GPP_F17 - GPIO */
|
||||
PAD_NC(GPP_F17, NONE),
|
||||
/* GPP_F18 - GPIO */
|
||||
PAD_NC(GPP_F18, NONE),
|
||||
/* GPP_F19 - GPIO */
|
||||
PAD_NC(GPP_F19, NONE),
|
||||
/* GPP_F20 - GPIO */
|
||||
PAD_NC(GPP_F20, NONE),
|
||||
/* GPP_F21 - GPIO */
|
||||
PAD_NC(GPP_F21, NONE),
|
||||
/* GPP_F22 - GPIO */
|
||||
PAD_NC(GPP_F22, NONE),
|
||||
/* GPP_F23 - NC */
|
||||
PAD_NC(GPP_F23, NONE),
|
||||
/* GPP_J0 - CNV_GNSS_PA_BLANKING */
|
||||
PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1),
|
||||
/* GPP_J1 - NC */
|
||||
PAD_NC(GPP_J1, NONE),
|
||||
/* GPP_J2 - NC */
|
||||
PAD_NC(GPP_J2, NONE),
|
||||
/* GPP_J3 - NC */
|
||||
PAD_NC(GPP_J3, NONE),
|
||||
|
||||
/* CNVi */
|
||||
/* GPP_J4 - CNV_BRI_DT*/
|
||||
PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1),
|
||||
/* GPP_J5 - CNV_BRI_RSP */
|
||||
PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1),
|
||||
/* GPP_J6 - CNV_RGI_DT */
|
||||
PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1),
|
||||
/* GPP_J7 - CNV_RGI_RSP */
|
||||
PAD_CFG_NF(GPP_J7, UP_20K, DEEP, NF1),
|
||||
/* GPP_J8 - CNV_MFUART2_RXD */
|
||||
PAD_CFG_NF(GPP_J8, NONE, DEEP, NF1),
|
||||
/* GPP_J9 - CNV_MFUART2_TXD */
|
||||
PAD_CFG_NF(GPP_J9, NONE, DEEP, NF1),
|
||||
|
||||
PAD_NC(GPP_J10, NONE),
|
||||
PAD_NC(GPP_J11, NONE),
|
||||
|
||||
/* Display Port */
|
||||
PAD_CFG_NF(GPP_I0, NONE, DEEP, NF1), /* DP1_HPD */
|
||||
PAD_CFG_NF(GPP_I1, NONE, DEEP, NF1), /* DP2_HPD */
|
||||
PAD_CFG_NF(GPP_I2, NONE, DEEP, NF1), /* DP3_HPD */
|
||||
PAD_NC(GPP_I3, NONE),
|
||||
PAD_NC(GPP_I4, NONE),
|
||||
|
||||
PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1), /* DP1_DDC_SCL */
|
||||
PAD_CFG_NF(GPP_I6, NONE, DEEP, NF1), /* DP1_DDC_SDA */
|
||||
|
||||
PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1), /* DP2_DDC_SCL */
|
||||
PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1), /* DP2_DDC_SDA */
|
||||
|
||||
PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1), /* DP3_DDC_SCL */
|
||||
PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1), /* DP3_DDC_SDA */
|
||||
|
||||
PAD_NC(GPP_I11, NONE),
|
||||
PAD_NC(GPP_I12, NONE),
|
||||
PAD_NC(GPP_I13, NONE),
|
||||
PAD_NC(GPP_I14, NONE),
|
||||
|
||||
};
|
||||
|
||||
/* Early pad configuration in bootblock. */
|
||||
const struct pad_config early_gpio_table[] = {
|
||||
/* Get PCIe out of reset */
|
||||
PAD_CFG_GPO(GPP_K0, 1, DEEP), /* PERST_PCH_SLOTS_n */
|
||||
PAD_CFG_GPO(GPP_K1, 1, DEEP), /* PERST_CPU_SLOTS_n */
|
||||
PAD_CFG_GPO(GPP_K2, 1, DEEP), /* PERST_CNVI_SLOTS_n */
|
||||
|
||||
/* SMB */
|
||||
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* PCH_SMB_CLK */
|
||||
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* PCH_SMB_DATA */
|
||||
PAD_NC(GPP_C2, NONE),
|
||||
|
||||
/* BMC HSI */
|
||||
PAD_CFG_GPI(GPP_K12, NONE, DEEP), /* PCH_IO_2 */
|
||||
PAD_CFG_GPI(GPP_K13, NONE, DEEP), /* PCH_IO_3 */
|
||||
PAD_CFG_GPI(GPP_K14, NONE, DEEP), /* PCH_IO_1 */
|
||||
PAD_NC(GPP_K15, NONE),
|
||||
PAD_CFG_GPI(GPP_K16, NONE, DEEP), /* PCH_IO_0 */
|
||||
|
||||
/* LED */
|
||||
PAD_CFG_GPO(GPP_H5, 0, DEEP), /* PCH_HBLED_n */
|
||||
};
|
||||
|
||||
const struct pad_config *get_gpio_table(size_t *num)
|
||||
{
|
||||
*num = ARRAY_SIZE(gpio_table);
|
||||
return gpio_table;
|
||||
}
|
||||
|
||||
const struct pad_config *get_early_gpio_table(size_t *num)
|
||||
{
|
||||
*num = ARRAY_SIZE(early_gpio_table);
|
||||
return early_gpio_table;
|
||||
}
|
||||
|
|
@ -0,0 +1,33 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#include <soc/ramstage.h>
|
||||
|
||||
#define HOSTC 0x40
|
||||
#define SMBUS_IO_BASE 0xefa0
|
||||
#define HOSTC_I2C_EN (1 << 2)
|
||||
#define I2C_ADDR_EEPROM 0x57
|
||||
|
||||
#if ENV_ROMSTAGE
|
||||
#define FSP_UPD_SIGNATURE FSPM_UPD_SIGNATURE
|
||||
#define EEPROM_OFFSET_FSP_SIGNATURE 0
|
||||
#define EEPROM_OFFSET_FSP_CONFIG 0
|
||||
|
||||
#define GET_VALUE(x) {.offset = sizeof(FSP_UPD_HEADER) + sizeof(FSPM_ARCH_UPD) \
|
||||
+ offsetof(FSP_M_CONFIG, x), .size = member_size(FSP_M_CONFIG, x)}
|
||||
#else
|
||||
|
||||
#define FSP_UPD_SIGNATURE FSPS_UPD_SIGNATURE
|
||||
#define EEPROM_OFFSET_FSP_SIGNATURE 0x0600
|
||||
#define EEPROM_OFFSET_FSP_CONFIG (EEPROM_OFFSET_FSP_SIGNATURE + sizeof(FSP_UPD_HEADER))
|
||||
#define GET_VALUE(x) {.offset = offsetof(FSP_S_CONFIG, x), \
|
||||
.size = member_size(FSP_S_CONFIG, x)}
|
||||
#endif // ENV_ROMSTAGE
|
||||
|
||||
typedef struct {
|
||||
size_t offset;
|
||||
size_t size;
|
||||
} fsp_params;
|
||||
|
||||
bool read_write_config(u8 addr, void *blob, size_t read_offset, size_t write_offset,
|
||||
size_t size);
|
||||
int check_signature(u8 addr);
|
||||
|
|
@ -0,0 +1,12 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef PCH_GPIO_H
|
||||
#define PCH_GPIO_H
|
||||
|
||||
#include <soc/gpio.h>
|
||||
#include <intelblocks/gpio_defs.h>
|
||||
|
||||
const struct pad_config *get_gpio_table(size_t *num);
|
||||
const struct pad_config *get_early_gpio_table(size_t *num);
|
||||
|
||||
#endif /* PCH_GPIO_H */
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
#include <soc/cnl_memcfg_init.h>
|
||||
|
||||
/* Return memory configuration structure. */
|
||||
const struct cnl_mb_cfg *variant_memcfg_config(void);
|
||||
|
|
@ -0,0 +1,193 @@
|
|||
chip soc/intel/cannonlake
|
||||
|
||||
device cpu_cluster 0 on
|
||||
device lapic 0 on end
|
||||
end
|
||||
|
||||
# FSP configuration
|
||||
|
||||
register "SataMode" = "0" # AHCI
|
||||
register "SataSalpSupport" = "0"
|
||||
register "SataPortsDevSlp[1]" = "1" # PCH_M2_SATA_DEVSLP1
|
||||
|
||||
register "SataPortsEnable[0]" = "1"
|
||||
register "SataPortsEnable[1]" = "1" # depends on SATAXPCIE1
|
||||
register "SataPortsEnable[2]" = "0" # Not used for SATA
|
||||
register "SataPortsEnable[3]" = "0" # Not used for SATA
|
||||
register "SataPortsEnable[4]" = "1"
|
||||
register "SataPortsEnable[5]" = "1"
|
||||
register "SataPortsEnable[6]" = "1"
|
||||
register "SataPortsEnable[7]" = "1"
|
||||
|
||||
register "PchHdaDspEnable" = "0"
|
||||
register "PchHdaAudioLinkHda" = "1"
|
||||
|
||||
# Enumeration starts at 0 for PCIE1
|
||||
# Ports are not hotplugable
|
||||
register "PcieRpEnable[0]" = "1" # Slot3 x4
|
||||
# Set MaxPayload to 256 bytes
|
||||
register "PcieRpMaxPayload[0]" = "RpMaxPayload_256"
|
||||
# Enable Latency Tolerance Reporting Mechanism
|
||||
register "PcieRpLtrEnable[0]" = "1"
|
||||
# Enable Advanced Error Reporting
|
||||
register "PcieRpAdvancedErrorReporting[0]" = "1"
|
||||
# Disable Aspm
|
||||
register "PcieRpAspm[0]" = "AspmDisabled"
|
||||
|
||||
|
||||
register "PcieRpEnable[4]" = "1" # PHY ETH3
|
||||
register "PcieRpEnable[5]" = "1" # PHY ETH4
|
||||
register "PcieRpEnable[6]" = "1" # PHY ETH2
|
||||
register "PcieRpEnable[7]" = "1" # PHY ETH1
|
||||
register "PcieRpEnable[8]" = "1" # M2 Slot M x4, depends on SATAXPCIE1
|
||||
register "PcieRpEnable[13]" = "1" # PHY ETH0
|
||||
register "PcieRpEnable[14]" = "1" # BMC
|
||||
register "PcieRpEnable[15]" = "1" # M2 Slot E x1
|
||||
register "PcieRpEnable[20]" = "1" # Slot 1 x4
|
||||
# Set MaxPayload to 256 bytes
|
||||
register "PcieRpMaxPayload[20]" = "RpMaxPayload_256"
|
||||
# Enable Latency Tolerance Reporting Mechanism
|
||||
register "PcieRpLtrEnable[20]" = "1"
|
||||
# Enable Advanced Error Reporting
|
||||
register "PcieRpAdvancedErrorReporting[20]" = "1"
|
||||
# Disable Aspm
|
||||
register "PcieRpAspm[20]" = "AspmDisabled"
|
||||
|
||||
# Controls the CLKREQ, not the output directly.
|
||||
# Depends on the CLKREQ to CLK gen mapping below
|
||||
register "PcieClkSrcUsage[0]" = "PCIE_CLK_FREE" # BMC, PCIe Slot1, Slot2, Slot4, Slot6
|
||||
register "PcieClkSrcUsage[1]" = "PCIE_CLK_FREE" # PHY3
|
||||
register "PcieClkSrcUsage[2]" = "PCIE_CLK_NOTUSED"
|
||||
register "PcieClkSrcUsage[3]" = "PCIE_CLK_NOTUSED"
|
||||
register "PcieClkSrcUsage[4]" = "PCIE_CLK_FREE" # RP9 M2 Slot M x4
|
||||
register "PcieClkSrcUsage[5]" = "PCIE_CLK_FREE" # RP16 M2 Slot E x1
|
||||
register "PcieClkSrcUsage[6]" = "PCIE_CLK_NOTUSED"
|
||||
register "PcieClkSrcUsage[7]" = "PCIE_CLK_NOTUSED"
|
||||
register "PcieClkSrcUsage[8]" = "PCIE_CLK_NOTUSED"
|
||||
register "PcieClkSrcUsage[9]" = "PCIE_CLK_NOTUSED"
|
||||
register "PcieClkSrcUsage[10]" = "PCIE_CLK_NOTUSED"
|
||||
register "PcieClkSrcUsage[11]" = "PCIE_CLK_NOTUSED"
|
||||
register "PcieClkSrcUsage[12]" = "PCIE_CLK_NOTUSED"
|
||||
register "PcieClkSrcUsage[13]" = "PCIE_CLK_FREE" # PHY 0, PHY 1, PHY 2, PHY 4
|
||||
register "PcieClkSrcUsage[14]" = "PCIE_CLK_FREE" # PB
|
||||
register "PcieClkSrcUsage[15]" = "PCIE_CLK_FREE" # PCIe Slot3
|
||||
|
||||
# Only map M2 CLKREQ to CLK gen
|
||||
register "PcieClkSrcClkReq[4]" = "4" # M2_M_CLK_REQ_n
|
||||
register "PcieClkSrcClkReq[5]" = "5" # M2_E_CLK_REQ_n
|
||||
|
||||
# USB Config 2.0/3.0
|
||||
# Enumeration starts at 0
|
||||
# USB 3.0
|
||||
# USB OC0: RP1
|
||||
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"
|
||||
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"
|
||||
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"
|
||||
register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)"
|
||||
|
||||
# USB OC1: RP2
|
||||
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)"
|
||||
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)"
|
||||
register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC1)"
|
||||
register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC1)"
|
||||
|
||||
# USB OC2: Internal Header CN_USB3_HDR
|
||||
register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)"
|
||||
register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC2)"
|
||||
register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC2)"
|
||||
register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC2)"
|
||||
|
||||
# USB 2.0
|
||||
# USB OC3: Internal Header USB2_HDR1
|
||||
register "usb2_ports[6]" = "USB2_PORT_MID(OC3)"
|
||||
register "usb2_ports[7]" = "USB2_PORT_MID(OC3)"
|
||||
|
||||
# USB OC4: Internal Header USB2_HDR2
|
||||
register "usb2_ports[8]" = "USB2_PORT_MID(OC4)"
|
||||
register "usb2_ports[9]" = "USB2_PORT_MID(OC4)"
|
||||
|
||||
# USB OC5-7: not connected
|
||||
# BMC
|
||||
register "usb2_ports[10]" = "USB2_PORT_MID(OC_SKIP)"
|
||||
# unused
|
||||
register "usb2_ports[11]" = "USB2_PORT_EMPTY"
|
||||
# piggy-back
|
||||
register "usb2_ports[12]" = "USB2_PORT_MID(OC_SKIP)"
|
||||
# M2 key E
|
||||
register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)"
|
||||
|
||||
# Thermal
|
||||
register "tcc_offset" = "6" # TCC of 94C
|
||||
|
||||
# Enable "Intel Speed Shift Technology"
|
||||
register "speed_shift_enable" = "1"
|
||||
|
||||
# HECI
|
||||
register "HeciEnabled" = "1"
|
||||
|
||||
# Internal GFX
|
||||
register "InternalGfx" = "1"
|
||||
|
||||
# Disable S0ix
|
||||
register "s0ix_enable" = "0"
|
||||
|
||||
register "common_soc_config" = "{
|
||||
.gspi[0] = {
|
||||
.speed_mhz = 1,
|
||||
.early_init = 1,
|
||||
},
|
||||
}"
|
||||
|
||||
# VR Power Delivery Design
|
||||
register "VrPowerDeliveryDesign" = "0x12"
|
||||
|
||||
register "SerialIoDevMode" = "{
|
||||
[PchSerialIoIndexI2C0] = PchSerialIoDisabled,
|
||||
[PchSerialIoIndexI2C1] = PchSerialIoDisabled,
|
||||
[PchSerialIoIndexI2C2] = PchSerialIoDisabled,
|
||||
[PchSerialIoIndexI2C3] = PchSerialIoDisabled,
|
||||
[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
|
||||
[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
|
||||
[PchSerialIoIndexSPI0] = PchSerialIoPci,
|
||||
[PchSerialIoIndexSPI1] = PchSerialIoDisabled,
|
||||
[PchSerialIoIndexUART0] = PchSerialIoPci,
|
||||
[PchSerialIoIndexUART1] = PchSerialIoPci,
|
||||
[PchSerialIoIndexUART2] = PchSerialIoPci,
|
||||
}"
|
||||
|
||||
register "DisableHeciRetry" = "1"
|
||||
|
||||
|
||||
device domain 0 on
|
||||
device pci 02.0 on end # Integrated Graphics Device
|
||||
chip drivers/intel/wifi
|
||||
register "wake" = "PME_B0_EN_BIT"
|
||||
device pci 14.3 on end # CNVi wifi
|
||||
end
|
||||
|
||||
device pci 19.2 on end # UART #2
|
||||
|
||||
device pci 1b.4 on
|
||||
smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT1" "SlotDataBusWidth4X"
|
||||
end # PCIe Slot 1
|
||||
device pci 1c.0 on
|
||||
smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT3" "SlotDataBusWidth4X"
|
||||
end # PCIe Slot 3
|
||||
device pci 1c.4 on end # PHY 3
|
||||
device pci 1c.5 on end # PHY 4
|
||||
device pci 1c.6 on end # PHY 2
|
||||
device pci 1c.7 on end # PHY 1
|
||||
|
||||
device pci 1d.0 on
|
||||
smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "M2 M" "SlotDataBusWidth4X"
|
||||
end # M2 M
|
||||
device pci 1d.5 on end # PHY 0
|
||||
device pci 1d.6 on end # BMC
|
||||
|
||||
device pci 1e.0 on end # UART #0
|
||||
device pci 1e.1 on end # UART #1
|
||||
device pci 1e.2 off end # GSPI #0
|
||||
device pci 1e.3 off end # GSPI #1
|
||||
|
||||
end
|
||||
end
|
||||
Loading…
Reference in New Issue