mb/google/brya/var/taniks: Modify DPTF settings for taniks
Update DPTF settings provided by thermal team BUG=b:215033682 TEST=build and tested on taniks board Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: Ic6860980b06e876dd4c21af26752ab6c1a3f7fff Reviewed-on: https://review.coreboot.org/c/coreboot/+/61337 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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@ -127,31 +127,31 @@ chip soc/intel/alderlake
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[1] = {
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.target = DPTF_TEMP_SENSOR_1,
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.thresholds = {
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TEMP_PCT(51, 74),
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TEMP_PCT(47, 60),
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TEMP_PCT(57, 70),
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TEMP_PCT(54, 60),
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TEMP_PCT(48, 60),
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TEMP_PCT(45, 45),
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TEMP_PCT(42, 45),
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TEMP_PCT(37, 35),
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TEMP_PCT(42, 39),
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}
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},
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[2] = {
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.target = DPTF_TEMP_SENSOR_2,
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.thresholds = {
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TEMP_PCT(51, 74),
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TEMP_PCT(47, 60),
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TEMP_PCT(57, 40),
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TEMP_PCT(54, 60),
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TEMP_PCT(48, 60),
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TEMP_PCT(45, 45),
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TEMP_PCT(42, 45),
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TEMP_PCT(37, 35),
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TEMP_PCT(42, 39),
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}
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},
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[3] = {
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.target = DPTF_TEMP_SENSOR_3,
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.thresholds = {
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TEMP_PCT(51, 74),
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TEMP_PCT(47, 60),
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TEMP_PCT(57, 70),
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TEMP_PCT(54, 60),
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TEMP_PCT(48, 60),
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TEMP_PCT(45, 45),
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TEMP_PCT(42, 45),
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TEMP_PCT(37, 35),
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TEMP_PCT(42, 39),
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}
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}
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}"
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@ -177,7 +177,7 @@ chip soc/intel/alderlake
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register "controls.power_limits" = "{
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.pl1 = {
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.min_power = 3000,
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.max_power = 12000,
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.max_power = 15000,
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.time_window_min = 28 * MSECS_PER_SEC,
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.time_window_max = 32 * MSECS_PER_SEC,
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.granularity = 200,
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@ -204,11 +204,11 @@ chip soc/intel/alderlake
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[0] = { 100, 6000, 220, 2200, },
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[1] = { 92, 5500, 180, 1800, },
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[2] = { 85, 5000, 145, 1450, },
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[3] = { 74, 4620, 115, 1150, },
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[4] = { 60, 4290, 90, 900, },
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[5] = { 45, 3980, 55, 550, },
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[6] = { 35, 3170, 30, 300, },
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[7] = { 30, 2640, 15, 150, },
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[3] = { 70, 4400, 115, 1150, },
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[4] = { 60, 3900, 90, 900, },
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[5] = { 45, 3300, 55, 550, },
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[6] = { 39, 3000, 30, 300, },
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[7] = { 33, 2900, 15, 150, },
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[8] = { 10, 800, 10, 100, },
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[9] = { 0, 0, 0, 50, }
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}"
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