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mb/google/brya/var/taniks: Modify DPTF settings for taniks 

Update DPTF settings provided by thermal team

BUG=b:215033682
TEST=build and tested on taniks board

Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: Ic6860980b06e876dd4c21af26752ab6c1a3f7fff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61337
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Joey Peng 2022-01-24 16:16:15 +08:00 committed by Felix Held
parent 51ede8af2e
commit b65c3015b0
1 changed files with 18 additions and 18 deletions
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36
src/mainboard/google/brya/variants/taniks/overridetree.cb
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@ -127,31 +127,31 @@ chip soc/intel/alderlake
[1] = { [1] = {
.target = DPTF_TEMP_SENSOR_1, .target = DPTF_TEMP_SENSOR_1,
.thresholds = { .thresholds = {
TEMP_PCT(51, 74), TEMP_PCT(57, 70),
TEMP_PCT(47, 60), TEMP_PCT(54, 60),
TEMP_PCT(48, 60),
TEMP_PCT(45, 45), TEMP_PCT(45, 45),
TEMP_PCT(42, 45), TEMP_PCT(42, 39),
TEMP_PCT(37, 35),
} }
}, },
[2] = { [2] = {
.target = DPTF_TEMP_SENSOR_2, .target = DPTF_TEMP_SENSOR_2,
.thresholds = { .thresholds = {
TEMP_PCT(51, 74), TEMP_PCT(57, 40),
TEMP_PCT(47, 60), TEMP_PCT(54, 60),
TEMP_PCT(48, 60),
TEMP_PCT(45, 45), TEMP_PCT(45, 45),
TEMP_PCT(42, 45), TEMP_PCT(42, 39),
TEMP_PCT(37, 35),
} }
}, },
[3] = { [3] = {
.target = DPTF_TEMP_SENSOR_3, .target = DPTF_TEMP_SENSOR_3,
.thresholds = { .thresholds = {
TEMP_PCT(51, 74), TEMP_PCT(57, 70),
TEMP_PCT(47, 60), TEMP_PCT(54, 60),
TEMP_PCT(48, 60),
TEMP_PCT(45, 45), TEMP_PCT(45, 45),
TEMP_PCT(42, 45), TEMP_PCT(42, 39),
TEMP_PCT(37, 35),
} }
} }
}" }"
@ -177,7 +177,7 @@ chip soc/intel/alderlake
register "controls.power_limits" = "{ register "controls.power_limits" = "{
.pl1 = { .pl1 = {
.min_power = 3000, .min_power = 3000,
.max_power = 12000, .max_power = 15000,
.time_window_min = 28 * MSECS_PER_SEC, .time_window_min = 28 * MSECS_PER_SEC,
.time_window_max = 32 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC,
.granularity = 200, .granularity = 200,
@ -204,11 +204,11 @@ chip soc/intel/alderlake
[0] = { 100, 6000, 220, 2200, }, [0] = { 100, 6000, 220, 2200, },
[1] = { 92, 5500, 180, 1800, }, [1] = { 92, 5500, 180, 1800, },
[2] = { 85, 5000, 145, 1450, }, [2] = { 85, 5000, 145, 1450, },
[3] = { 74, 4620, 115, 1150, }, [3] = { 70, 4400, 115, 1150, },
[4] = { 60, 4290, 90, 900, }, [4] = { 60, 3900, 90, 900, },
[5] = { 45, 3980, 55, 550, }, [5] = { 45, 3300, 55, 550, },
[6] = { 35, 3170, 30, 300, }, [6] = { 39, 3000, 30, 300, },
[7] = { 30, 2640, 15, 150, }, [7] = { 33, 2900, 15, 150, },
[8] = { 10, 800, 10, 100, }, [8] = { 10, 800, 10, 100, },
[9] = { 0, 0, 0, 50, } [9] = { 0, 0, 0, 50, }
}" }"