soc/intel: Consolidate FSP CAR setup and teardown code
This patch adds following changes,
- APL, CFL, DENVERTON soc's using same implementation to setup and
teardown FSP CAR. Hence cache_as_ram_fsp.S from soc folder is
cosolidated into one file and moved to common code CPU car folder.
- exit_car_fsp.S is from APL, DNV soc folder is clubbed into one file
and moved to common CPU car.
- The new file apollolake/fspcar.c is addded to pass tempraminit
parameters.
- Coffee lake Soc uses FSPT to support Intel Security features like
BootGuard verify boot and Measured boot. Add FSP CAR support for CFL
by programming tempraminit parameters and add FSP_T_XIP default if
FSP_CAR is selected.
BUG= None
TEST= Build for both CFL RVP11 & RVP8 and verified for successful CAR setup.
Build for both leafhill and harcuvar platform by selecting CONFIG_FSP_CAR
without errors.
Change-Id: I98d2dd9711ddc0d7ea7d1672fba700259ee3a3a9
Signed-off-by: Praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>
Reviewed-on: https://review.coreboot.org/29209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Praveen hodagatta pranesh
Patrick Georgi
parent
ac6a5080ec
commit
b66757fc58
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@ -9,6 +9,7 @@ subdirs-y += ../../../cpu/x86/tsc
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subdirs-y += ../../../cpu/x86/cache
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bootblock-y += bootblock/bootblock.c
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bootblock-$(CONFIG_FSP_CAR) += fspcar.c
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bootblock-y += car.c
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bootblock-y += heci.c
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bootblock-y += gspi.c
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@ -18,7 +19,6 @@ bootblock-y += mmap_boot.c
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bootblock-y += pmutil.c
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bootblock-y += spi.c
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bootblock-$(CONFIG_UART_DEBUG) += uart.c
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bootblock-$(CONFIG_FSP_CAR) += bootblock/cache_as_ram_fsp.S
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romstage-y += car.c
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romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage.c
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@ -76,8 +76,6 @@ postcar-$(CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE) += heci.c
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postcar-$(CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE) += reset.c
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postcar-$(CONFIG_UART_DEBUG) += uart.c
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postcar-$(CONFIG_FSP_CAR) += exit_car_fsp.S
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verstage-y += car.c
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verstage-y += i2c.c
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verstage-y += gspi.c
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@ -1,110 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015-2016 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <device/pci_def.h>
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/cache.h>
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#include <cpu/x86/cr.h>
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#include <cpu/x86/post_code.h>
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#include <../../../arch/x86/walkcbfs.S>
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#define FSP_HDR_OFFSET 0x94
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.global bootblock_pre_c_entry
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bootblock_pre_c_entry:
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.global cache_as_ram
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cache_as_ram:
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post_code(0x21)
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/* find fsp in cbfs */
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lea fsp_name, %esi
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mov $1f, %esp
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jmp walkcbfs_asm
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1:
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cmp $0, %eax
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jz .halt_forever
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mov CBFS_FILE_OFFSET(%eax), %ebx
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bswap %ebx
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add %eax, %ebx
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add FSP_HDR_OFFSET, %ebx
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/*
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* ebx = FSP INFO HEADER
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* Calculate entry into FSP
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*/
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mov 0x30(%ebx), %eax /* Load TempRamInitEntryOffset */
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add 0x1c(%ebx), %eax /* add the FSP ImageBase */
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/*
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* Pass early init variables on a fake stack (no memory yet)
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* as well as the return location
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*/
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lea CAR_init_stack, %esp
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/* call FSP binary to setup temporary stack */
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jmp *%eax
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/*
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* If the TempRamInit API is successful, then when returning, the ECX and
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* EDX registers will point to the temporary but writeable memory range
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* available to the bootloader where ECX is the start and EDX is the end of
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* the range i.e. [ECX,EDX). See Apollo Lake FSP Integration Guide for more
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* information.
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*
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* Return Values:
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* EAX | Return Status
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* ECX | Temporary Memory Start
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* EDX | Temporary Memory End
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* EBX, EDI, ESI, EBP, MM0, MM1 | Preserved Through API Call
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*/
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CAR_init_done:
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/* Setup bootblock stack */
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mov %edx, %esp
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/* clear CAR_GLOBAL area as it is not shared */
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cld
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xor %eax, %eax
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movl $(_car_global_end), %ecx
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movl $(_car_global_start), %edi
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sub %edi, %ecx
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rep stosl
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/* We can call into C functions now */
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call bootblock_c_entry
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/* Never reached */
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.halt_forever:
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post_code(POST_DEAD_CODE)
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hlt
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jmp .halt_forever
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CAR_init_params:
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.long 0 /* Microcode Location */
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.long 0 /* Microcode Length */
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.long 0xFFFFFFFF - CONFIG_ROM_SIZE + 1 /* Firmware Location */
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.long CONFIG_ROM_SIZE /* Total Firmware Length */
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CAR_init_stack:
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.long CAR_init_done
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.long CAR_init_params
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fsp_name:
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.ascii "blobs/fspt.bin\x00"
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@ -0,0 +1,35 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2018 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <bootblock_common.h>
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#include <FsptUpd.h>
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const FSPT_UPD temp_ram_init_params = {
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.FspUpdHeader = {
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.Signature = 0x545F4450554C5041ULL, /* 'APLUPD_T' */
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.Revision = 1,
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.Reserved = {0},
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},
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.FsptCommonUpd = {
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.Revision = 0,
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.Reserved = {0},
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.MicrocodeRegionBase = 0,
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.MicrocodeRegionLength = 0,
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.CodeRegionBase =
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(uint32_t)(0x100000000ULL - CONFIG_ROM_SIZE),
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.CodeRegionLength = (uint32_t)CONFIG_ROM_SIZE,
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.Reserved1 = {0},
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},
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};
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@ -75,6 +75,7 @@ config CPU_SPECIFIC_OPTIONS
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select UDELAY_TSC
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select UDK_2017_BINDING
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select DISPLAY_FSP_VERSION_INFO
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select FSP_T_XIP if FSP_CAR
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config UART_DEBUG
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bool "Enable UART debug port."
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@ -1,7 +1,7 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2017 Intel Corporation..
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* Copyright (C) 2017-2018 Intel Corporation..
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -19,6 +19,24 @@
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#include <soc/bootblock.h>
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#include <soc/iomap.h>
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#include <soc/pch.h>
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#include <FsptUpd.h>
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const FSPT_UPD temp_ram_init_params = {
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.FspUpdHeader = {
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.Signature = 0x545F4450554C4643ULL, /* 'CFLUPD_T' */
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.Revision = 1,
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.Reserved = {0},
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},
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.FsptCoreUpd = {
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.MicrocodeRegionBase =
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(uint32_t)CONFIG_CPU_MICROCODE_CBFS_LOC,
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.MicrocodeRegionSize =
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(uint32_t)CONFIG_CPU_MICROCODE_CBFS_LEN,
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.CodeRegionBase =
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(uint32_t)(0x100000000ULL - CONFIG_ROM_SIZE),
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.CodeRegionSize = (uint32_t)CONFIG_ROM_SIZE,
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},
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};
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asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
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{
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@ -1,10 +1,12 @@
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bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CAR) += car/cache_as_ram.S
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bootblock-$(CONFIG_FSP_CAR)+= car/cache_as_ram_fsp.S
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bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU) += cpulib.c
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romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CAR) += car/exit_car.S
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romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU) += cpulib.c
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postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CAR) += car/exit_car.S
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postcar-$(CONFIG_FSP_CAR) += car/exit_car_fsp.S
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ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU) += cpulib.c
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ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT) += mp_init.c
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@ -1,7 +1,7 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015 - 2017 Intel Corp.
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* Copyright (C) 2018 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -19,10 +19,8 @@
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#include <cpu/x86/cache.h>
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#include <cpu/x86/cr.h>
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#include <cpu/x86/post_code.h>
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#include <../../../../../arch/x86/walkcbfs.S>
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#include <../../../arch/x86/walkcbfs.S>
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#define FSP_HDR_OFFSET 0x94
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.extern temp_ram_init_params
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@ -31,7 +29,7 @@ bootblock_pre_c_entry:
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.global cache_as_ram
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cache_as_ram:
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post_code(0x2f)
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post_code(0x21)
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/* find fsp in cbfs */
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lea fsp_name, %esi
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@ -43,8 +41,7 @@ cache_as_ram:
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mov CBFS_FILE_OFFSET(%eax), %ebx
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bswap %ebx
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add %eax, %ebx
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addl $FSP_HDR_OFFSET, %ebx
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add $0x94, %ebx
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/*
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* save mm2 into ebp, because TempRamInit API doesn't preserve
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@ -72,8 +69,7 @@ cache_as_ram:
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* If the TempRamInit API is successful, then when returning, the ECX and
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* EDX registers will point to the temporary but writeable memory range
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* available to the bootloader where ECX is the start and EDX is the end of
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* the range i.e. [ECX,EDX). See Denverton_ns FSP Integration Guide for more
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* information.
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* the range i.e. [ECX,EDX). See FSP Integration Guide for more information.
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*
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* Return Values:
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* EAX | Return Status
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@ -86,6 +82,9 @@ CAR_init_done:
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cmp $0, %eax
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jnz .halt_forever
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/* Setup bootblock stack */
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mov %edx, %esp
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/* clear CAR_GLOBAL area as it is not shared */
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cld
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xor %eax, %eax
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@ -95,9 +94,6 @@ CAR_init_done:
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shrl $2, %ecx
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rep stosl
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/* Setup bootblock stack */
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movl $(_car_stack_end), %esp
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/* Restore the timestamp from bootblock_crt0.S (ebp:mm1) */
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push %ebp
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movd %mm1, %eax
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@ -113,10 +109,9 @@ CAR_init_done:
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hlt
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jmp .halt_forever
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.align 4
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CAR_init_stack:
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.long CAR_init_done
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.long temp_ram_init_params
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fsp_name:
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.ascii "fspt.bin\x00"
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.string "fspt.bin"
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@ -1,7 +1,7 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2016 Intel Corp.
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* Copyright (C) 2018 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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@ -23,16 +23,8 @@
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* the rest of arch/x86/exit_car.S and calls main() itself instead of
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* returning to _start. In main(), the TempRamExit FSP API is called
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* to tear down the CAR and set up caching which can be overwritten
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* after the API call. More info can be found in the Apollo Lake FSP
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* Integration Guide included with the FSP binary. The below
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* caching settings are based on an 8MiB Flash Size given as a
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* parameter to TempRamInit.
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*
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* TempRamExit MTRR Settings:
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* 0x00000000 - 0x0009FFFF | Write Back
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* 0x000C0000 - Top of Low Memory | Write Back
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* 0xFF800000 - 0xFFFFFFFF Flash Reg | Write Protect
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* 0x100000000 - Top of High Memory | Write Back
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* after the API call. More info can be found in the FSP Integration
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* Guide included with the FSP binary.
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*/
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.text
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@ -23,7 +23,6 @@ subdirs-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm
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subdirs-y += ../../../cpu/x86/tsc
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subdirs-y += ../../../cpu/x86/cache
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bootblock-$(CONFIG_FSP_CAR)+= bootblock/cache_as_ram_fsp.S
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bootblock-y += bootblock/bootblock.c
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bootblock-y += spi.c
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bootblock-y += tsc_freq.c
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@ -31,7 +30,6 @@ bootblock-$(CONFIG_CONSOLE_SERIAL) += bootblock/uart.c
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bootblock-$(CONFIG_DRIVERS_UART_8250MEM) += uart_debug.c
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postcar-y += memmap.c
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postcar-$(CONFIG_FSP_CAR) += exit_car_fsp.S
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postcar-y += spi.c
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postcar-$(CONFIG_DRIVERS_UART_8250MEM) += uart_debug.c
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@ -1,47 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2016-2017 Intel Corp.
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*
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||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; version 2 of
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||||
* the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
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||||
*/
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/cr.h>
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//#include <soc/cpu.h>
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/*
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* This path for CAR teardown is taken when CONFIG_FSP_CAR is employed.
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* This version of chipset_teardown_car sets up the stack, then bypasses
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* the rest of arch/x86/exit_car.S and calls main() itself instead of
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* returning to _start. In main(), the TempRamExit FSP API is called
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* to tear down the CAR and set up caching which can be overwritten
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* after the API call. More info can be found in the Denverton-NS FSP
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* Integration Guide included with the FSP binary. The below
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* caching settings are based on an 8MiB Flash Size given as a
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* parameter to TempRamInit.
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*
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* TempRamExit MTRR Settings:
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* 0x00000000 - 0x0009FFFF | Write Back
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* 0x000C0000 - Top of Low Memory | Write Back
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* 0xFF800000 - 0xFFFFFFFF Flash Reg | Write Protect
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* 0x100000000 - Top of High Memory | Write Back
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*/
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.text
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.global chipset_teardown_car
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chipset_teardown_car:
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/* Set up new stack. */
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mov post_car_stack_top, %esp
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/* Call C code */
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call main
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