skylake: add support for verstage

The right files just need to be added to the verstage
build. Do that so a stand alone verstage builds and
links.

BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built and booted glados.

Change-Id: I2d0c98760494e2f4657ee35b6f155690939d2d18
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11827
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

src/soc/intel/common/Makefile.inc

@@ -1,5 +1,7 @@
 ifeq ($(CONFIG_SOC_INTEL_COMMON),y)
 
+verstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c
+
 romstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c
 romstage-$(CONFIG_SOC_INTEL_COMMON_FSP_RAM_INIT) += raminit.c
 romstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c

src/soc/intel/skylake/Makefile.inc

@@ -8,6 +8,15 @@ subdirs-y += ../../../cpu/x86/mtrr
 subdirs-y += ../../../cpu/x86/smm
 subdirs-y += ../../../cpu/x86/tsc
 
+verstage-y += gpio.c
+verstage-y += memmap.c
+verstage-y += monotonic_timer.c
+verstage-y += pch.c
+verstage-y += pmutil.c
+verstage-y += pcr.c
+verstage-y += tsc_freq.c
+verstage-$(CONFIG_UART_DEBUG) += uart_debug.c
+
 romstage-y += flash_controller.c
 romstage-y += gpio.c
 romstage-y += memmap.c

src/soc/intel/skylake/romstage/Makefile.inc

@@ -1,3 +1,12 @@
+verstage-y += cpu.c
+verstage-y += pch.c
+verstage-y += report_platform.c
+verstage-y += romstage.c
+verstage-y += smbus.c
+verstage-y += spi.c
+verstage-y += systemagent.c
+verstage-y += uart.c
+
 romstage-y += cpu.c
 romstage-y += pch.c
 romstage-y += power_state.c