Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage handling for Fam 10 in SVI mode. I don't understand what this was doing nor find docs for these regs Maybe it was left over from some copy & paste ? Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6411 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -16,8 +16,93 @@
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/*
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* This file initializes the CPU cores for voltage and frequency settings
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* in the different power states.
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*/
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/*
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checklist (functions are in this file if no source file named)
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Fam10 Bios and Kernel Development Guide #31116, rev 3.48, April 22, 2010
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2.4.2.6 Requirements for p-states
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1.- F3x[84:80] According to table 100 : prep_fid_change
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2.- COF/VID :
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2.4.2.9.1 Steps 1,3-6 and warning for 2,7 if they apply
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fixPsNbVidBeforeWR(...)
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2.4.2.9.1 Step 8 enable_fid_change
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We do this for all nodes, I don't understand BKDG 100% on
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whether this is or isn't meant by "on the local
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processor". Must be OK.
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2.4.2.9.1 Steps 9-10 (repeat 1-7 and reset) romstage.c/init_cpus ?
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2.4.2.9.1 Steps 11-12 init_fidvid_stage2
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2.4.2.9.2 DualPlane PVI : Not supported, don't know how to detect,
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needs specific circuitry.
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3.- 2.4.2.7 dualPlaneOnly(dev)
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4.- 2.4.2.8 applyBoostFIDOffset(dev)
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5.- enableNbPState1(dev)
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6.- 2.4.1.7
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a) UpdateSinglePlaneNbVid()
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b) setVSRamp(), called from prep_fid_change
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c) prep_fid_change
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d) improperly, for lack of voltage regulator details?,
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F3xA0[PsiVidEn] in defaults.h
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F3xA0[PsiVid] in init_cpus.c AMD_SetupPSIVID_d (before prep_fid_change)
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7.- TODO (Core Performance Boost is only available in revision E cpus, and we
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don't seem to support those yet, at least they don't have any
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constant in amddefs.h )
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8.- FIXME ? Transition to min Pstate according to 2.4.2.15.3 is required
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by 2.4.2.6 after warm reset. But 2.4.2.15 states that it is not required
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if the warm reset is issued by coreboot to update NbFid. So it is required
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or not ? How can I tell who issued warm reset ?
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Coreboot transitions to P0 instead, which is not recommended, and does
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not follow 2.4.2.15.2 to do so.
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9.- TODO Requires information on current delivery capability
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(depends on mainboard and maybe power supply ?). One might use a config
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option with the maximum number of Ampers that the board can deliver to CPU.
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10.- [Multiprocessor] TODO 2.4.2.12
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[Uniprocessor] FIXME ? We call setPStateMaxVal() in init_fidvid_stage2,
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but not sure this is what is meant by "Determine the valid set of
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P-states based on enabled P-states indicated
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in MSRC001_00[68:64][PstateEn]" in 2.4.2.6-10
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11.- finalPstateChange() from init_fidvid_Stage2 (BKDG says just "may", anyway)
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12.- generate ACPI for p-states. FIXME
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Needs more assesment. There's some kind of fixed support that
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does not seem to depend on CPU revision or actual MSRC001_00[68:64]
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as BKDG apparently requires.
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http://www.coreboot.org/ACPI#CPU_Power_Management
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At least for Tilapia board:
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src/mainboard/<vendor>/<model>/acpi_tables.c write_acpi_tables(...) calls
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acpi_add_ssdt_pstates(...)
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in /src/northbridge/amd/amdfam10/amdfam10_acpi.c
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which apparently copies them from static info in
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src/mainboard/<vendor>/<model>/acpi/cpstate.asl
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"must also be completed"
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a.- PllLockTime set in ruleset in defaults.h
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BKDG says set it "If MSRC001_00[68:64][CpuFid] is different between
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any two enabled P-states", but since it does not say "only if"
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I guess it is safe to do it always.
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b.- prep_fid_change(...)
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*/
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#if CONFIG_SET_FIDVID
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#include <northbridge/amd/amdht/AsPsDefs.h>
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static inline void print_debug_fv(const char *str, u32 val)
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