GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

ck804: obtain I/O APIC base address for ACPI MADT from allocator 

Change-Id: I67192c8ae99e396ea4b17e03c658f31dbb5c1800
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/3960
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
Jonathan A. Kollasch 2013-10-11 14:58:39 -05:00
parent 3fa1a13f62
commit b679525538
4 changed files with 60 additions and 48 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

25
src/mainboard/msi/ms7135/acpi_tables.c
View File

@ -48,28 +48,29 @@ unsigned long acpi_fill_mcfg(unsigned long current)
/* APIC */ /* APIC */
unsigned long acpi_fill_madt(unsigned long current) unsigned long acpi_fill_madt(unsigned long current)
{ {
unsigned long apic_addr;
device_t dev; device_t dev;
struct resource *res;
/* create all subtables for processors */ /* create all subtables for processors */
current = acpi_create_madt_lapics(current); current = acpi_create_madt_lapics(current);
/* Write NVIDIA CK804 IOAPIC. */ /* Write NVIDIA CK804 IOAPIC. */
dev = dev_find_slot(0x0, PCI_DEVFN(0x1,0)); dev = dev_find_slot(0x0, PCI_DEVFN(0x1,0));
if (dev) { ASSERT(dev != NULL);
apic_addr = pci_read_config32(dev, PCI_BASE_ADDRESS_1) & ~0xf;
current += acpi_create_madt_ioapic( res = find_resource(dev, PCI_BASE_ADDRESS_1);
(acpi_madt_ioapic_t *)current, ASSERT(res != NULL);
CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS,
apic_addr, 0); current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current,
/* Initialize interrupt mapping if mptable.c didn't. */ CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS, res->base, 0);
/* Initialize interrupt mapping if mptable.c didn't. */
#if (!CONFIG_GENERATE_MP_TABLE) #if (!CONFIG_GENERATE_MP_TABLE)
#error untested config #error untested config
pci_write_config32(dev, 0x7c, 0x0120d218); pci_write_config32(dev, 0x7c, 0x0120d218);
pci_write_config32(dev, 0x80, 0x12008a00); pci_write_config32(dev, 0x80, 0x12008a00);
pci_write_config32(dev, 0x84, 0x0000007d); pci_write_config32(dev, 0x84, 0x0000007d);
#endif #endif
}
/* IRQ of timer */ /* IRQ of timer */
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)

21
src/mainboard/tyan/s2891/acpi_tables.c
View File

@ -32,23 +32,26 @@ unsigned long acpi_fill_madt(unsigned long current)
{ {
unsigned long apic_addr; unsigned long apic_addr;
device_t dev; device_t dev;
struct resource *res;
/* create all subtables for processors */ /* create all subtables for processors */
current = acpi_create_madt_lapics(current); current = acpi_create_madt_lapics(current);
/* Write NVIDIA CK804 IOAPIC. */ /* Write NVIDIA CK804 IOAPIC. */
dev = dev_find_slot(0x0, PCI_DEVFN(0x1,0)); dev = dev_find_slot(0x0, PCI_DEVFN(0x1,0));
if (dev) { ASSERT(dev != NULL);
apic_addr = pci_read_config32(dev, PCI_BASE_ADDRESS_1) & ~0xf;
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 4, res = find_resource(dev, PCI_BASE_ADDRESS_1);
apic_addr, 0); ASSERT(res != NULL);
/* Initialize interrupt mapping if mptable.c didn't. */
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 4,
res->base, 0);
/* Initialize interrupt mapping if mptable.c didn't. */
#if (!CONFIG_GENERATE_MP_TABLE) #if (!CONFIG_GENERATE_MP_TABLE)
pci_write_config32(dev, 0x7c, 0x0120d218); pci_write_config32(dev, 0x7c, 0x0120d218);
pci_write_config32(dev, 0x80, 0x12008a00); pci_write_config32(dev, 0x80, 0x12008a00);
pci_write_config32(dev, 0x84, 0x0000007d); pci_write_config32(dev, 0x84, 0x0000007d);
#endif #endif
}
/* Write AMD 8131 two IOAPICs. */ /* Write AMD 8131 two IOAPICs. */
dev = dev_find_slot(0x40, PCI_DEVFN(0x0,1)); dev = dev_find_slot(0x40, PCI_DEVFN(0x0,1));

21
src/mainboard/tyan/s2892/acpi_tables.c
View File

@ -32,23 +32,26 @@ unsigned long acpi_fill_madt(unsigned long current)
{ {
unsigned long apic_addr; unsigned long apic_addr;
device_t dev; device_t dev;
struct resource *res;
/* create all subtables for processors */ /* create all subtables for processors */
current = acpi_create_madt_lapics(current); current = acpi_create_madt_lapics(current);
/* Write NVIDIA CK804 IOAPIC. */ /* Write NVIDIA CK804 IOAPIC. */
dev = dev_find_slot(0x0, PCI_DEVFN(0x1,0)); dev = dev_find_slot(0x0, PCI_DEVFN(0x1,0));
if (dev) { ASSERT(dev != NULL);
apic_addr = pci_read_config32(dev, PCI_BASE_ADDRESS_1) & ~0xf;
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 4, res = find_resource(dev, PCI_BASE_ADDRESS_1);
apic_addr, 0); ASSERT(res != NULL);
/* Initialize interrupt mapping if mptable.c didn't. */
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 4,
res->base, 0);
/* Initialize interrupt mapping if mptable.c didn't. */
#if (!CONFIG_GENERATE_MP_TABLE) #if (!CONFIG_GENERATE_MP_TABLE)
pci_write_config32(dev, 0x7c, 0x0120d218); pci_write_config32(dev, 0x7c, 0x0120d218);
pci_write_config32(dev, 0x80, 0x12008a00); pci_write_config32(dev, 0x80, 0x12008a00);
pci_write_config32(dev, 0x84, 0x0000007d); pci_write_config32(dev, 0x84, 0x0000007d);
#endif #endif
}
/* Write AMD 8131 two IOAPICs. */ /* Write AMD 8131 two IOAPICs. */
dev = dev_find_slot(0x40, PCI_DEVFN(0x0,1)); dev = dev_find_slot(0x40, PCI_DEVFN(0x0,1));

41
src/mainboard/tyan/s2895/acpi_tables.c
View File

@ -32,23 +32,26 @@ unsigned long acpi_fill_madt(unsigned long current)
{ {
unsigned long apic_addr; unsigned long apic_addr;
device_t dev; device_t dev;
struct resource *res;
/* create all subtables for processors */ /* create all subtables for processors */
current = acpi_create_madt_lapics(current); current = acpi_create_madt_lapics(current);
/* Write NVIDIA CK804 IOAPIC. */ /* Write NVIDIA CK804 IOAPIC. */
dev = dev_find_slot(0x0, PCI_DEVFN(0x1,0)); dev = dev_find_slot(0x0, PCI_DEVFN(0x1,0));
if (dev) { ASSERT(dev != NULL);
apic_addr = pci_read_config32(dev, PCI_BASE_ADDRESS_1) & ~0xf;
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 4, res = find_resource(dev, PCI_BASE_ADDRESS_1);
apic_addr, 0); ASSERT(res != NULL);
/* Initialize interrupt mapping if mptable.c didn't. */
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 4,
res->base, 0);
/* Initialize interrupt mapping if mptable.c didn't. */
#if (!CONFIG_GENERATE_MP_TABLE) #if (!CONFIG_GENERATE_MP_TABLE)
pci_write_config32(dev, 0x7c, 0x0120d218); pci_write_config32(dev, 0x7c, 0x0120d218);
pci_write_config32(dev, 0x80, 0x12008a00); pci_write_config32(dev, 0x80, 0x12008a00);
pci_write_config32(dev, 0x84, 0x00080d7d); pci_write_config32(dev, 0x84, 0x00080d7d);
#endif #endif
}
/* Write AMD 8131 two IOAPICs. */ /* Write AMD 8131 two IOAPICs. */
dev = dev_find_slot(0x40, PCI_DEVFN(0x0,1)); dev = dev_find_slot(0x40, PCI_DEVFN(0x0,1));
@ -67,17 +70,19 @@ unsigned long acpi_fill_madt(unsigned long current)
/* Write second NVIDIA CK804 IOAPIC. */ /* Write second NVIDIA CK804 IOAPIC. */
dev = dev_find_slot(0x80, PCI_DEVFN(0x1, 0)); dev = dev_find_slot(0x80, PCI_DEVFN(0x1, 0));
if (dev) { ASSERT(dev != NULL);
apic_addr = pci_read_config32(dev, PCI_BASE_ADDRESS_1) & ~0xf;
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 7, res = find_resource(dev, PCI_BASE_ADDRESS_1);
apic_addr, 0x20); ASSERT(res != NULL);
/* Initialize interrupt mapping if mptable.c didn't. */
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 7,
res->base, 0x20);
/* Initialize interrupt mapping if mptable.c didn't. */
#if (!CONFIG_GENERATE_MP_TABLE) #if (!CONFIG_GENERATE_MP_TABLE)
pci_write_config32(dev, 0x7c, 0x0000d218); // Why does the factory BIOS have 0? pci_write_config32(dev, 0x7c, 0x0000d218); // Why does the factory BIOS have 0?
pci_write_config32(dev, 0x80, 0x00000000); pci_write_config32(dev, 0x80, 0x00000000);
pci_write_config32(dev, 0x84, 0x00000d00); // Same here. pci_write_config32(dev, 0x84, 0x00000d00); // Same here.
#endif #endif
}
/* IRQ9 */ /* IRQ9 */
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)