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soc/qualcomm: Drop unneeded empty lines 

Change-Id: If76502ff91896959ef171c192b4fc138dff18fc6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44599
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
This commit is contained in:
Elyes HAOUAS 2020-08-19 21:45:02 +02:00 committed by Michael Niewöhner
parent f91bcb310b
commit b69bbfe1ef
28 changed files with 0 additions and 44 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/soc/qualcomm/ipq40xx/gpio.c
View File

@ -17,7 +17,6 @@ static inline int gpio_not_valid(gpio_t gpio)
return (gpio > GPIO_MAX_NUM);
}
/*******************************************************
Function description: configure GPIO functinality
Arguments :
@ -30,7 +29,6 @@ unsigned enable - 0 Disable, 1 - Enable.
Return : None
*******************************************************/
void gpio_tlmm_config_set(gpio_t gpio, unsigned int func,
unsigned int pull, unsigned int drvstr,
unsigned int enable)
@ -60,7 +58,6 @@ unsigned *enable - 0 - Disable, 1- Enable.
Return : None
*******************************************************/
void gpio_tlmm_config_get(gpio_t gpio, unsigned int *func,
unsigned int *pull, unsigned int *drvstr,
unsigned int *enable)
@ -93,7 +90,6 @@ int gpio_get(gpio_t gpio)
if (gpio_not_valid(gpio))
return -1;
return (read32(GPIO_IN_OUT_ADDR(gpio)) >> GPIO_IO_IN_SHIFT) &
GPIO_IO_IN_MASK;
}

1
src/soc/qualcomm/ipq40xx/include/soc/blsp.h
View File

@ -1,6 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
#ifndef __BLSP_H_
#define __BLSP_H_

1
src/soc/qualcomm/ipq40xx/include/soc/cdp.h
View File

@ -1,6 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
#ifndef _IPQ40XX_CDP_H_
#define _IPQ40XX_CDP_H_

2
src/soc/qualcomm/ipq40xx/include/soc/clock.h
View File

@ -175,7 +175,6 @@
#define GMAC_COREn_CLCK_INV_DISABLE (0 << 5)
#define GMAC_COREn_CLCK_BRANCH_ENA (1 << 4)
/* Uart specific clock settings */
void uart_pll_vote_clk_enable(unsigned int);
@ -186,5 +185,4 @@ void usb_clock_config(void);
int audio_clock_config(unsigned int frequency);
int blsp_i2c_clock_config(blsp_qup_id_t id);
#endif /* __PLATFORM_IPQ40XX_CLOCK_H_ */

1
src/soc/qualcomm/ipq40xx/include/soc/ipq_uart.h
View File

@ -10,7 +10,6 @@
extern void __udelay(unsigned long usec);
enum MSM_BOOT_UART_DM_PARITY_MODE {
MSM_BOOT_UART_DM_NO_PARITY,
MSM_BOOT_UART_DM_ODD_PARITY,

2
src/soc/qualcomm/ipq40xx/include/soc/spi.h
View File

@ -134,7 +134,6 @@ struct blsp_spi {
void *qup_deassert_wait;
};
#define SUCCESS 0
#define DUMMY_DATA_VAL 0
@ -148,7 +147,6 @@ struct blsp_spi {
* (count function disabled) and does not hold significance in the count. */
#define MAX_PACKET_COUNT ((64 * KiB) - 1)
struct ipq_spi_slave {
struct spi_slave slave;
const struct blsp_spi *regs;

2
src/soc/qualcomm/ipq40xx/usb.c
View File

@ -44,14 +44,12 @@
#define DWC3_GSNPSID 0xc120
#define DWC3_DCTL 0xc704
/* Global USB2 PHY Configuration Register */
#define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31)
#define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6)
#define DWC3_GSNPSID_MASK 0xffff0000
#define DWC3_GEVTEN 0xc114
#define DWC3_GCTL_SCALEDOWN(n) ((n) << 4)
#define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3)
#define DWC3_GCTL_DISSCRAMBLE (1 << 3)

4
src/soc/qualcomm/ipq806x/gpio.c
View File

@ -17,7 +17,6 @@ static inline int gpio_not_valid(gpio_t gpio)
return (gpio > GPIO_MAX_NUM);
}
/*******************************************************
Function description: configure GPIO functinality
Arguments :
@ -30,7 +29,6 @@ unsigned enable - 0 Disable, 1 - Enable.
Return : None
*******************************************************/
void gpio_tlmm_config_set(gpio_t gpio, unsigned int func,
unsigned int pull, unsigned int drvstr,
unsigned int enable)
@ -60,7 +58,6 @@ unsigned *enable - 0 - Disable, 1- Enable.
Return : None
*******************************************************/
void gpio_tlmm_config_get(gpio_t gpio, unsigned int *func,
unsigned int *pull, unsigned int *drvstr,
unsigned int *enable)
@ -93,7 +90,6 @@ int gpio_get(gpio_t gpio)
if (gpio_not_valid(gpio))
return -1;
return (read32(GPIO_IN_OUT_ADDR(gpio)) >> GPIO_IO_IN_SHIFT) &
GPIO_IO_IN_MASK;
}

1
src/soc/qualcomm/ipq806x/include/soc/clock.h
View File

@ -156,7 +156,6 @@
#define GMAC_COREn_CLCK_INV_DISABLE (0 << 5)
#define GMAC_COREn_CLCK_BRANCH_ENA (1 << 4)
/* Uart specific clock settings */
void uart_pll_vote_clk_enable(unsigned int);

1
src/soc/qualcomm/ipq806x/include/soc/gsbi.h
View File

@ -1,6 +1,5 @@
/* SPDX-License-Identifier: ISC */
#ifndef __GSBI_H_
#define __GSBI_H_

1
src/soc/qualcomm/ipq806x/include/soc/iomap.h
View File

@ -122,7 +122,6 @@
#define GSBI_QUP_APPS_PRE_DIV_SFT 3
#define GSBI_QUP_APPS_SRC_SEL_MSK 0x7
#define GSBI_QUP_APSS_MD_REG(gsbi_n) ((MSM_CLK_CTL_BASE + 0x29c8) + \
(32*(gsbi_n-1)))
#define GSBI_QUP_APSS_NS_REG(gsbi_n) ((MSM_CLK_CTL_BASE + 0x29cc) + \

1
src/soc/qualcomm/ipq806x/include/soc/ipq_uart.h
View File

@ -11,7 +11,6 @@
extern void __udelay(unsigned long usec);
enum MSM_BOOT_UART_DM_PARITY_MODE {
MSM_BOOT_UART_DM_NO_PARITY,
MSM_BOOT_UART_DM_ODD_PARITY,

2
src/soc/qualcomm/ipq806x/spi.c
View File

@ -32,7 +32,6 @@
#define GSBI_IDX_TO_GSBI(idx) (idx + 5)
/* MX_INPUT_COUNT and MX_OUTPUT_COUNT are 16-bits. Zero has a special meaning
* (count function disabled) and does not hold significance in the count. */
#define MAX_PACKET_COUNT ((64 * KiB) - 1)
@ -141,7 +140,6 @@ static unsigned int qup_apps_clk_state[NUM_PORTS] = {
GSBI7_QUP_APPS_CLK
};
static int check_bit_state(uint32_t reg_addr, int bit_num, int val, int us_delay)
{
unsigned int count = TIMEOUT_CNT;

1
src/soc/qualcomm/qcs405/include/soc/addressmap.h
View File

@ -3,7 +3,6 @@
#ifndef __SOC_QUALCOMM_QCS405_ADDRESS_MAP_H__
#define __SOC_QUALCOMM_QCS405_ADDRESS_MAP_H__
#define QSPI_BASE 0x88DF000
#define TLMM_EAST_TILE_BASE 0x7B00000
#define TLMM_NORTH_TILE_BASE 0x1300000

1
src/soc/qualcomm/qcs405/include/soc/blsp.h
View File

@ -1,6 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
#ifndef __BLSP_H_
#define __BLSP_H_

1
src/soc/qualcomm/qcs405/include/soc/cdp.h
View File

@ -1,6 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
#ifndef _QCS405_CDP_H_
#define _QCS405_CDP_H_

1
src/soc/qualcomm/qcs405/include/soc/gpio.h
View File

@ -17,7 +17,6 @@ typedef struct {
#define TLMM_GPIO_IN_OUT_OFF 0x4
#define TLMM_GPIO_ID_STATUS_OFF 0x10
/* GPIO INTR CFG MASK */
#define GPIO_INTR_DECT_CTL_MASK 0x3
#define GPIO_INTR_RAW_STATUS_EN_MASK 0x1

1
src/soc/qualcomm/qcs405/include/soc/qup.h
View File

@ -3,7 +3,6 @@
#ifndef __QUP_H__
#define __QUP_H__
/* QUP block registers */
#define QUP_CONFIG 0x000
#define QUP_STATE 0x004

2
src/soc/qualcomm/qcs405/include/soc/spi.h
View File

@ -155,7 +155,6 @@ struct blsp_spi {
void *qup_deassert_wait;
};
#define SUCCESS 0
#define DUMMY_DATA_VAL 0
@ -169,7 +168,6 @@ struct blsp_spi {
* (count function disabled) and does not hold significance in the count. */
#define MAX_PACKET_COUNT ((64 * KiB) - 1)
struct qcs_spi_slave {
struct spi_slave slave;
const struct blsp_spi *regs;

1
src/soc/qualcomm/qcs405/include/soc/uart.h
View File

@ -10,7 +10,6 @@
extern void __udelay(unsigned long usec);
enum MSM_BOOT_UART_DM_PARITY_MODE {
MSM_BOOT_UART_DM_NO_PARITY,
MSM_BOOT_UART_DM_ODD_PARITY,

1
src/soc/qualcomm/qcs405/qup.c
View File

@ -60,7 +60,6 @@ static void i2c_set_mstr_clk_ctl(unsigned int id, unsigned int hz)
qup_write32(QUP_ADDR(id, QUP_I2C_MASTER_CLK_CTL), mstr_clk_ctl);
}
static qup_return_t qup_i2c_master_status(blsp_qup_id_t id)
{
uint32_t reg_val = read32(QUP_ADDR(id, QUP_I2C_MASTER_STATUS));

1
src/soc/qualcomm/qcs405/uart.c
View File

@ -89,7 +89,6 @@ static int valid_data = 0;
/* Received data */
static unsigned int word = 0;
void uart_tx_byte(unsigned int idx, unsigned char data)
{
int num_of_chars = 1;

1
src/soc/qualcomm/qcs405/usb.c
View File

@ -197,7 +197,6 @@ void setup_usb_host(enum usb_port port, struct usb_board_data *board_data)
/* Clear core reset. */
clock_reset_bcr(dwc3->usb3_bcr, 0);
if (port == HSUSB_SS_PORT_0) {
/* Set PHY reset. */
setbits32(&dwc3->usb2_phy_bcr, BIT(1));

1
src/soc/qualcomm/sc7180/include/soc/addressmap.h
View File

@ -3,7 +3,6 @@
#ifndef _SOC_QUALCOMM_SC7180_ADDRESS_MAP_H_
#define _SOC_QUALCOMM_SC7180_ADDRESS_MAP_H_
#define AOSS_CC_BASE 0x0C2A0000
#define GCC_BASE 0x00100000
#define QSPI_BASE 0x088DC000

1
src/soc/qualcomm/sc7180/include/soc/usb.h
View File

@ -79,5 +79,4 @@ void setup_usb_host0(struct usb_board_data *data);
/* Call reset_ before setup_ */
void reset_usb0(void);
#endif /* _SC7180_USB_H_ */

1
src/soc/qualcomm/sc7180/qupv3_config.c
View File

@ -52,7 +52,6 @@ void qupv3_se_fw_load_and_init(unsigned int bus, unsigned int protocol,
clrbits_le32(&regs->geni_cgc_ctrl, GENI_CGC_CTRL_PROG_RAM_SCLK_OFF_BMSK
| GENI_CGC_CTRL_PROG_RAM_HCLK_OFF_BMSK);
/* HPG section 3.1.7.1 */
if (protocol != SE_PROTOCOL_UART) {
setbits_le32(&regs->geni_dfs_if_cfg,

6
src/soc/qualcomm/sc7180/usb.c
View File

@ -290,8 +290,6 @@ static struct usb3_phy_qserdes_rx_reg_layout *const qserdes_rx_reg_layout =
static struct usb3_phy_pcs_reg_layout *const pcs_reg_layout =
(void *)QMP_PHY_PCS_REG_BASE;
struct usb_dwc3 {
u32 sbuscfg0;
u32 sbuscfg1;
@ -436,8 +434,6 @@ static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = {
{&pcs_reg_layout->pcs_rxeqtraining_run_time, 0x13},
};
struct usb_dwc3_cfg {
struct usb_dwc3 *usb_host_dwc3;
struct usb_qusb_phy_pll *qusb_phy_pll;
@ -481,7 +477,6 @@ static struct usb_dwc3_cfg usb_port0 = {
.efuse_offset = 25,
};
static struct qfprom_corr * const qfprom_corr_efuse = (void *)QFPROM_BASE;
static void reset_usb(struct usb_dwc3_cfg *dwc3)
@ -505,7 +500,6 @@ void reset_usb0(void)
reset_usb(&usb_port0);
}
/*
* Update board specific PHY tuning override values that specified from
* board file.

1
src/soc/qualcomm/sdm845/include/soc/addressmap.h
View File

@ -3,7 +3,6 @@
#ifndef __SOC_QUALCOMM_SDM845_ADDRESS_MAP_H__
#define __SOC_QUALCOMM_SDM845_ADDRESS_MAP_H__
#define QSPI_BASE 0x88DF000
#define TLMM_EAST_TILE_BASE 0x03500000
#define TLMM_NORTH_TILE_BASE 0x03900000