Example on how to add other chipsets to inteltool. ICH/ICH0, ICH4(-M) and ICH7
have different register meanings, so they get their own lookup tables. This is a trivial patch. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3307 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer
Stefan Reinauer
parent
1984067a86
commit
b69e46bca3
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@ -34,6 +34,10 @@
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/* Tested Chipsets: */
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#define PCI_VENDOR_ID_INTEL 0x8086
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#define PCI_DEVICE_ID_INTEL_ICH 0x2410
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#define PCI_DEVICE_ID_INTEL_ICH0 0x2420
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#define PCI_DEVICE_ID_INTEL_ICH4 0x24c0
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#define PCI_DEVICE_ID_INTEL_ICH4M 0x24cc
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#define PCI_DEVICE_ID_INTEL_ICH7 0x27b8
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#define PCI_DEVICE_ID_INTEL_82945GM 0x27a0
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@ -45,35 +49,89 @@ int fd_msr;
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typedef struct { uint32_t hi, lo; } msr_t;
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typedef struct { uint16_t addr; int size; char *name; } io_register_t;
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static const io_register_t ich0_gpio_registers[] = {
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{ 0x00, 4, "GPIO_USE_SEL" },
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{ 0x04, 4, "GP_IO_SEL" },
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{ 0x08, 4, "RESERVED" },
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{ 0x0c, 4, "GP_LVL" },
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{ 0x10, 4, "RESERVED" },
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{ 0x14, 4, "GPO_TTL" },
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{ 0x18, 4, "GPO_BLINK" },
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{ 0x1c, 4, "RESERVED" },
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{ 0x20, 4, "RESERVED" },
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{ 0x24, 4, "RESERVED" },
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{ 0x28, 4, "RESERVED" },
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{ 0x2c, 4, "GPI_INV" },
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{ 0x30, 4, "RESERVED" },
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{ 0x34, 4, "RESERVED" },
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{ 0x38, 4, "RESERVED" },
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{ 0x3C, 4, "RESERVED" }
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};
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static const io_register_t ich4_gpio_registers[] = {
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{ 0x00, 4, "GPIO_USE_SEL" },
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{ 0x04, 4, "GP_IO_SEL" },
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{ 0x08, 4, "RESERVED" },
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{ 0x0c, 4, "GP_LVL" },
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{ 0x10, 4, "RESERVED" },
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{ 0x14, 4, "GPO_TTL" },
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{ 0x18, 4, "GPO_BLINK" },
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{ 0x1c, 4, "RESERVED" },
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{ 0x20, 4, "RESERVED" },
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{ 0x24, 4, "RESERVED" },
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{ 0x28, 4, "RESERVED" },
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{ 0x2c, 4, "GPI_INV" },
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{ 0x30, 4, "GPIO_USE_SEL2" },
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{ 0x34, 4, "GP_IO_SEL2" },
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{ 0x38, 4, "GP_LVL2" },
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{ 0x3C, 4, "RESERVED" }
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};
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static const io_register_t ich7_gpio_registers[] = {
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{ 0x00, 4, "GPIO_USE_SEL" },
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{ 0x04, 4, "GP_IO_SEL" },
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{ 0x08, 4, "RESERVED" },
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{ 0x0c, 4, "GP_LVL" },
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{ 0x10, 4, "RESERVED" },
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{ 0x14, 4, "RESERVED" },
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{ 0x18, 4, "GPO_BLINK" },
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{ 0x1c, 4, "RESERVED" },
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{ 0x20, 4, "RESERVED" },
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{ 0x24, 4, "RESERVED" },
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{ 0x28, 4, "RESERVED" },
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{ 0x2c, 4, "GPI_INV" },
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{ 0x30, 4, "GPIO_USE_SEL2" },
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{ 0x34, 4, "GP_IO_SEL2" },
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{ 0x38, 4, "GP_LVL2" },
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{ 0x3C, 4, "RESERVED" }
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};
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int print_gpios(struct pci_dev *sb)
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{
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int i;
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int i, size;
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uint16_t gpiobase;
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io_register_t ich7_gpio_registers[] = {
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{ 0x00, 4, "GPIO_USE_SEL" },
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{ 0x04, 4, "GP_IO_SEL" },
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{ 0x08, 4, "RESERVED" },
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{ 0x0c, 4, "GP_LVL" },
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{ 0x10, 4, "RESERVED" },
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{ 0x14, 4, "RESERVED" },
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{ 0x18, 4, "GPO_BLINK" },
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{ 0x1c, 4, "RESERVED" },
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{ 0x20, 4, "RESERVED" },
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{ 0x24, 4, "RESERVED" },
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{ 0x28, 4, "RESERVED" },
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{ 0x2c, 4, "GPI_INV" },
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{ 0x30, 4, "GPIO_USE_SEL2" },
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{ 0x34, 4, "GP_IO_SEL2" },
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{ 0x38, 4, "GP_LVL2" },
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{ 0x3C, 4, "RESERVED" }
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};
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const io_register_t *gpio_registers;
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printf("\n============= GPIOS =============\n\n");
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switch (sb->device_id) {
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case PCI_DEVICE_ID_INTEL_ICH7:
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gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
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gpio_registers = ich7_gpio_registers;
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size = ARRAY_SIZE(ich7_gpio_registers);
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break;
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case PCI_DEVICE_ID_INTEL_ICH4:
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case PCI_DEVICE_ID_INTEL_ICH4M:
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gpiobase = pci_read_word(sb, 0x58) & 0xfffc;
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gpio_registers = ich4_gpio_registers;
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size = ARRAY_SIZE(ich4_gpio_registers);
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break;
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case PCI_DEVICE_ID_INTEL_ICH:
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case PCI_DEVICE_ID_INTEL_ICH0:
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gpiobase = pci_read_word(sb, 0x58) & 0xfffc;
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gpio_registers = ich0_gpio_registers;
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size = ARRAY_SIZE(ich0_gpio_registers);
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break;
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case 0x1234: // Dummy for non-existent functionality
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printf("Error: This southbridge does not have GPIOBASE.\n");
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@ -85,25 +143,25 @@ int print_gpios(struct pci_dev *sb)
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printf("GPIOBASE = 0x%04x (IO)\n\n", gpiobase);
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for (i=0; i<ARRAY_SIZE(ich7_gpio_registers); i++) {
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switch (ich7_gpio_registers[i].size) {
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for (i=0; i<size; i++) {
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switch (gpio_registers[i].size) {
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case 4:
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printf("gpiobase+0x%04x: 0x%08x (%s)\n",
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ich7_gpio_registers[i].addr,
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inl(gpiobase+ich7_gpio_registers[i].addr),
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ich7_gpio_registers[i].name);
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gpio_registers[i].addr,
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inl(gpiobase+gpio_registers[i].addr),
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gpio_registers[i].name);
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break;
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case 2:
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printf("gpiobase+0x%04x: 0x%04x (%s)\n",
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ich7_gpio_registers[i].addr,
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inw(gpiobase+ich7_gpio_registers[i].addr),
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ich7_gpio_registers[i].name);
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gpio_registers[i].addr,
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inw(gpiobase+gpio_registers[i].addr),
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gpio_registers[i].name);
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break;
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case 1:
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printf("gpiobase+0x%04x: 0x%02x (%s)\n",
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ich7_gpio_registers[i].addr,
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inb(gpiobase+ich7_gpio_registers[i].addr),
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ich7_gpio_registers[i].name);
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gpio_registers[i].addr,
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inb(gpiobase+gpio_registers[i].addr),
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gpio_registers[i].name);
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break;
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}
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}
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@ -123,7 +181,10 @@ int print_rcba(struct pci_dev *sb)
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case PCI_DEVICE_ID_INTEL_ICH7:
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rcba_phys = pci_read_long(sb, 0xf0) & 0xfffffffe;
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break;
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case 0x1234: // Dummy for non-existent functionality
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case PCI_DEVICE_ID_INTEL_ICH:
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case PCI_DEVICE_ID_INTEL_ICH0:
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case PCI_DEVICE_ID_INTEL_ICH4:
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case PCI_DEVICE_ID_INTEL_ICH4M:
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printf("Error: This southbridge does not have RCBA.\n");
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return 1;
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default:
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@ -635,7 +696,11 @@ int main(int argc, char *argv[])
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char * name;
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} supported_chips_list[] = {
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945GM, "i945" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7, "ICH7" }
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7, "ICH7" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH4M, "ICH4-M" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH4, "ICH4" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH0, "ICH0" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH, "ICH" }
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};
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while ((opt = getopt_long(argc, argv, "vh?gmrpedPca",
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