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soc/intel/jasperlake: Remove DDI A lane programming 

For newer Intel graphics (>=11), the DDI port max lanes default to 4.
And kernel driver no longer relies on coreboot to provide information
via DDI_BUF_CTL_A (for DDI port A) register programming. Hence removing
this code.

BUG=b:150788968
BRANCH=None
TEST=checked jslrvp compilation and boot.
Change-Id: I4c171ec6a57d6fc53bee88420bfb3c0fbc5dc057
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40038
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Ronak Kanabar 2020-04-02 16:03:41 +05:30 committed by Nico Huber
parent e8d483923b
commit b6a523927d
1 changed files with 0 additions and 19 deletions
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19
src/soc/intel/jasperlake/graphics.c
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@ -19,7 +19,6 @@
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ops.h>
#include <drivers/intel/gma/i915_reg.h>
#include <drivers/intel/gma/opregion.h>
#include <intelblocks/graphics.h>
#include <types.h>
@ -31,24 +30,6 @@ uintptr_t fsp_soc_get_igd_bar(void)
void graphics_soc_init(struct device *dev)
{
uint32_t ddi_buf_ctl;
/* Skip IGD GT programming */
if (CONFIG(SKIP_GRAPHICS_ENABLING))
return;
/*
* Enable DDI-A (eDP) 4-lane operation if the link is not up yet.
* This will allow the kernel to use 4-lane eDP links properly
* if the VBIOS or GOP driver do not execute.
*/
ddi_buf_ctl = graphics_gtt_read(DDI_BUF_CTL_A);
if (!acpi_is_wakeup_s3() && !(ddi_buf_ctl & DDI_BUF_CTL_ENABLE)) {
ddi_buf_ctl |= (DDI_A_4_LANES | DDI_INIT_DISPLAY_DETECTED |
DDI_BUF_IS_IDLE);
graphics_gtt_write(DDI_BUF_CTL_A, ddi_buf_ctl);
}
/*
* GFX PEIM module inside FSP binary is taking care of graphics
* initialization based on RUN_FSP_GOP Kconfig