kahlee: Set Kahlee GPEs

Add GPE configuration table.

Remove GPE3 from the power button ASL and set the EC to GPE3(AGPIO22).

Set the EC and PCIE/WLAN SCI GPIO signals.

Set GPE ASL methods for:
  PCIE/WLAN      8h
  EHCI          18h
  XHCI          1fh
Note EC GPE3 methods are in the EC ASL.

BUG=b:63268311
BRANCH=none
TEST=Test lidswitch powers the device on and off at the login screen.

Change-Id: I27c880ee84b6797d999d4d5951602b654ede948e
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22096
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/google/kahlee/acpi/gpe.asl

@@ -15,63 +15,26 @@
 
 Scope (\_GPE)
 {
-	/*  General event 3  */
+	/*  PCIE WLAN Wake event  */
-	Method (_L03)
-	{
-		/* DBGO ("\\_GPE\\_L00\n") */
-		Notify (\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
-	}
-
-	/*  Legacy PM event  */
 	Method (_L08)
 	{
 		/* DBGO ("\\_GPE\\_L08\n") */
-	}
-
-	/*  Temp warning (TWarn) event  */
-	Method (_L09)
-	{
-		/* DBGO ("\\_GPE\\_L09\n") */
-		/* Notify (\_TZ.TZ00, 0x80) */
-	}
-
-	/*  USB controller PME#  */
-	Method (_L0B)
-	{
-		/* DBGO ("\\_GPE\\_L0B\n") */
-		Notify (\_SB.PCI0.EHC0, 0x02)	/* NOTIFY_DEVICE_WAKE */
-		Notify (\_SB.PCI0.XHC0, 0x02)	/* NOTIFY_DEVICE_WAKE */
 		Notify (\_SB.PWRB, 0x02)	/* NOTIFY_DEVICE_WAKE */
 	}
 
-	/*  ExtEvent0 SCI event  */
+	/*  EHCI USB controller PME#  SCIMAP24*/
-	Method (_L10)
-	{
-		/* DBGO ("\\_GPE\\_L10\n") */
-	}
-
-	/*  ExtEvent1 SCI event  */
-	Method (_L11)
-	{
-		/* DBGO ("\\_GPE\\_L11\n") */
-	}
-
-	/*  GPIO0 or GEvent8 event  */
 	Method (_L18)
 	{
 		/* DBGO ("\\_GPE\\_L18\n") */
-		Notify (\_SB.PCI0.PBR4, 0x02)	/* NOTIFY_DEVICE_WAKE */
+		Notify (\_SB.PCI0.EHC0, 0x02)	/* NOTIFY_DEVICE_WAKE */
-		Notify (\_SB.PCI0.PBR5, 0x02)	/* NOTIFY_DEVICE_WAKE */
-		Notify (\_SB.PCI0.PBR6, 0x02)	/* NOTIFY_DEVICE_WAKE */
-		Notify (\_SB.PCI0.PBR7, 0x02)	/* NOTIFY_DEVICE_WAKE */
 		Notify (\_SB.PWRB, 0x02)	/* NOTIFY_DEVICE_WAKE */
 	}
 
-	/*  Azalia SCI event  */
+	/*  XHCI USB controller PME#  SCIMAP56*/
-	Method (_L1B)
+	Method (_L1F)
 	{
-		/* DBGO("\\_GPE\\_L1B\n") */
+		/* DBGO ("\\_GPE\\_L1F\n") */
-		Notify (\_SB.PCI0.AZHD, 0x02)	/* NOTIFY_DEVICE_WAKE */
+		Notify (\_SB.PCI0.XHC0, 0x02)	/* NOTIFY_DEVICE_WAKE */
 		Notify (\_SB.PWRB, 0x02)	/* NOTIFY_DEVICE_WAKE */
 	}
 }	/* End Scope GPE */

src/mainboard/google/kahlee/dsdt.asl

@@ -59,8 +59,6 @@ DefinitionBlock (
 		Device(PWRB) {
 			Name(_HID, EISAID("PNP0C0C"))
 			Name(_UID, 0xAA)
-			Name(_PRW, Package () {3, 0x04})
-			Name(_STA, 0x0B)
 		}
 
 		Device(PCI0) {

src/mainboard/google/kahlee/ec.h

@@ -19,8 +19,8 @@
 #include <ec/ec.h>
 #include <ec/google/chromeec/ec_commands.h>
 
-/* GPIO_S0_000 is EC_SCI#, but it is bit 24 in GPE_STS */
+/* AGPIO22 -> GPE3 */
-#define EC_SCI_GPI   24
+#define EC_SCI_GPI   3
 /* GPIO_S5_07 is EC_SMI#, but it is bit 23 in GPE_STS and ALT_GPIO_SMI. */
 #define EC_SMI_GPI   23
 

src/mainboard/google/kahlee/gpio.c

@@ -15,10 +15,15 @@
 
 #include <AGESA.h>
 #include <FchPlatform.h>
+#include <mainboard.h>
+#include <soc/smi.h>
 #include <soc/southbridge.h>
 #include <stdlib.h>
 
 const GPIO_CONTROL oem_kahlee_gpio[] = {
+	/* AGPIO2 PCIE/WLAN WAKE# SCI*/
+	{2, Function1, FCH_GPIO_PULL_UP_ENABLE },
+
 	/* SER TX */
 	{8, Function1, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE
 						| FCH_GPIO_OUTPUT_ENABLE},
@@ -45,6 +50,8 @@ const GPIO_CONTROL oem_kahlee_gpio[] = {
 	/* APU_I2C_3_SDA */
 	{20, Function1, FCH_GPIO_PULL_UP_ENABLE },
 
+	/* AGPIO22 EC_SCI */
+	{22, Function1, FCH_GPIO_PULL_UP_ENABLE },
 
 	/* APU_BT_ON# */
 	{24, Function1, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE
@@ -91,3 +98,48 @@ const GPIO_CONTROL oem_kahlee_gpio[] = {
 
 	{-1}
 };
+
+/*
+ * GPE setup table must match ACPI GPE ASL
+ *  { gevent, gpe, direction, level }
+ */
+static const struct sci_source gpe_table[] = {
+
+	/* EC AGPIO22/Gevent3 -> GPE 3 */
+	{
+		.scimap = 3,
+		.gpe = 3,
+		.direction = SMI_SCI_LVL_LOW,
+		.level = SMI_SCI_EDG,
+	},
+
+	/* PCIE/WLAN AGPIO2/Gevent8 -> GPE8 */
+	{
+		.scimap = 8,
+		.gpe = 8,
+		.direction = SMI_SCI_LVL_LOW,
+		.level = SMI_SCI_LVL,
+	},
+
+	/* EHCI USB_PME -> GPE24 */
+	{
+		.scimap = 24,
+		.gpe = 24,
+		.direction = SMI_SCI_LVL_HIGH,
+		.level = SMI_SCI_LVL,
+	},
+
+	/* XHCIC0 -> GPE31 */
+	{
+		.scimap = 56,
+		.gpe = 31,
+		.direction = SMI_SCI_LVL_HIGH,
+		.level = SMI_SCI_LVL,
+	},
+};
+
+const struct sci_source *get_gpe_table(size_t *num)
+{
+	*num = ARRAY_SIZE(gpe_table);
+	return gpe_table;
+}

src/mainboard/google/kahlee/mainboard.c

@@ -19,6 +19,8 @@
 #include <agesawrapper.h>
 #include <amd_pci_util.h>
 #include <ec.h>
+#include <mainboard.h>
+#include <soc/smi.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 
 /***********************************************************
@@ -79,7 +81,13 @@ static void pirq_setup(void)
 
 static void mainboard_init(void *chip_info)
 {
+	const struct sci_source *gpes;
+	size_t num;
+
 	mainboard_ec_init();
+
+	gpes = get_gpe_table(&num);
+	gpe_configure_sci(gpes, num);
 }
 
 /*************************************************

src/mainboard/google/kahlee/mainboard.h

@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef MAINBOARD_H
+#define MAINBOARD_H
+
+#include <soc/smi.h>
+
+const struct sci_source *get_gpe_table(size_t *num);
+
+#endif /* MAINBOARD_H */