console/flashconsole: Enable support for postcar

If FSP 2.0 is used, then postcar stage is used and the flashconsole
as well as spi drivers needed to be added.

Change-Id: I46d720a9d1fe18a95c9407d08dae1eb70ae6720e
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/21959
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/drivers/spi/Makefile.inc

@@ -11,6 +11,7 @@ ifeq ($(CONFIG_CONSOLE_SPI_FLASH),y)
 bootblock-y += flashconsole.c
 romstage-y += flashconsole.c
 ramstage-y += flashconsole.c
+postcar-y += flashconsole.c
 smm-$(CONFIG_DEBUG_SMI) += flashconsole.c
 
 endif
@@ -98,3 +99,7 @@ smm-$(CONFIG_SPI_FLASH_STMICRO) += stmicro.c
 smm-$(CONFIG_SPI_FLASH_WINBOND) += winbond.c
 smm-$(CONFIG_SPI_FRAM_RAMTRON) += ramtron.c
 endif
+
+postcar-y += spi-generic.c
+postcar-$(CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY) += boot_device_rw_nommap.c
+postcar-$(CONFIG_SPI_FLASH) += spi_flash.c

src/soc/intel/common/block/gspi/Makefile.inc

@@ -2,3 +2,4 @@ bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI) += gspi.c
 romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI) += gspi.c
 ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI) += gspi.c
 verstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI) += gspi.c
+postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI) += gspi.c

src/soc/intel/skylake/Makefile.inc

@@ -82,6 +82,8 @@ smm-y += uart.c
 
 postcar-y += memmap.c
 postcar-$(CONFIG_UART_DEBUG) += uart_debug.c
+postcar-y += gspi.c
+postcar-y += spi.c
 
 # cpu_microcode_bins += ???