soc/intel/apollolake: enable RTC
BUG=none TEST=Boot to OS and verfiy if rtc0 device is created under /sys/class/rtc/ Change-Id: Idec569255859816fda467bb42a215c00f7c0e16e Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Reviewed-on: https://review.coreboot.org/14883 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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@ -15,13 +15,17 @@
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* GNU General Public License for more details.
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*/
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#include <cbmem.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <pc80/mc146818rtc.h>
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#include <soc/acpi.h>
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#include <soc/lpc.h>
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#include <soc/pci_ids.h>
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#include <soc/pm.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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#include "chip.h"
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@ -43,6 +47,25 @@
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* opens up IO and memory windows as needed.
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*/
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static void rtc_init(void)
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{
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int rtc_fail;
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const struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE);
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if (!ps) {
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printk(BIOS_ERR, "Could not find power state in cbmem, RTC init aborted\n");
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return;
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}
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rtc_fail = !!(ps->gen_pmcon1 & RPS);
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/* Ensure the date is set including century byte. */
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cmos_check_update_date();
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if (IS_ENABLED(CONFIG_CHROMEOS_VBNV_CMOS))
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init_vbnv_cmos(rtc_fail);
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else
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cmos_init(rtc_fail);
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}
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static void lpc_init(struct device *dev)
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{
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uint8_t scnt;
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@ -61,6 +84,9 @@ static void lpc_init(struct device *dev)
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else if (cfg->serirq_mode == SERIRQ_CONTINUOUS)
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scnt |= SCNT_EN | SCNT_MODE;
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pci_write_config8(dev, REG_SERIRQ_CTL, scnt);
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/* Initialize RTC */
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rtc_init();
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}
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static void soc_lpc_add_io_resources(device_t dev)
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