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Rework i855GM/i855GME support 

Signed-off-by: Andreas Schultz <aschultz@tpip.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>

---
 src/northbridge/intel/i855/Kconfig       |   30 +
 src/northbridge/intel/i855/i855.h        |   76 +++
 src/northbridge/intel/i855/northbridge.c |   21 +
 src/northbridge/intel/i855/raminit.c     | 1036 +++++++++++++++++++++++++-----
 src/northbridge/intel/i855/raminit.h     |   14 +-
 5 files changed, 1002 insertions(+), 175 deletions(-)
 create mode 100644 src/northbridge/intel/i855/i855.h





git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5751 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Andreas Schultz 2010-08-30 16:19:04 +00:00 committed by Stefan Reinauer
parent 1bab1fb839
commit b6b29dbbb9
4 changed files with 955 additions and 204 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

30
src/northbridge/intel/i855/Kconfig
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@ -1,3 +1,33 @@
config NORTHBRIDGE_INTEL_I855 config NORTHBRIDGE_INTEL_I855
bool bool
select HAVE_DEBUG_RAM_SETUP
choice
prompt "Onboard graphics"
default I855_VIDEO_MB_8MB
depends on NORTHBRIDGE_INTEL_I855
config I855_VIDEO_MB_OFF
bool "Disabled, 0KB"
config I855_VIDEO_MB_1MB
bool "Enabled, 1MB"
config I855_VIDEO_MB_4MB
bool "Enabled, 4MB"
config I855_VIDEO_MB_8MB
bool "Enabled, 8MB"
config I855_VIDEO_MB_16MB
bool "Enabled, 16MB"
config I855_VIDEO_MB_32MB
bool "Enabled, 32MB"
endchoice
config VIDEO_MB
int
default 0 if I855_VIDEO_MB_OFF
default 1 if I855_VIDEO_MB_1MB
default 4 if I855_VIDEO_MB_4MB
default 8 if I855_VIDEO_MB_8MB
default 16 if I855_VIDEO_MB_16MB
default 32 if I855_VIDEO_MB_32MB
depends on NORTHBRIDGE_INTEL_I855

21
src/northbridge/intel/i855/northbridge.c
View File

@ -25,6 +25,7 @@
#include <stdint.h> #include <stdint.h>
#include <device/device.h> #include <device/device.h>
#include <device/pci.h> #include <device/pci.h>
#include <device/pci_ids.h>
#include <stdlib.h> #include <stdlib.h>
#include <string.h> #include <string.h>
#include <bitops.h> #include <bitops.h>
@ -32,6 +33,26 @@
#include <cpu/cpu.h> #include <cpu/cpu.h>
#include "chip.h" #include "chip.h"
static void northbridge_init(device_t dev)
{
printk(BIOS_SPEW, "Northbridge init\n");
}
static struct device_operations northbridge_operations = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = northbridge_init,
.enable = 0,
.ops_pci = 0,
};
static const struct pci_driver northbridge_driver __pci_driver = {
.ops = &northbridge_operations,
.vendor = PCI_VENDOR_ID_INTEL,
.device = 0x3580,
};
static void ram_resource(device_t dev, unsigned long index, static void ram_resource(device_t dev, unsigned long index,
unsigned long basek, unsigned long sizek) unsigned long basek, unsigned long sizek)
{ {

1094
src/northbridge/intel/i855/raminit.c
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File diff suppressed because it is too large Load Diff

14
src/northbridge/intel/i855/raminit.h
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@ -18,11 +18,19 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/ */
#ifndef RAMINIT_H #ifndef NORTHBRIDGE_INTEL_I855_RAMINIT_H
#define RAMINIT_H #define NORTHBRIDGE_INTEL_I855_RAMINIT_H
/* i855 Northbridge PCI device */
#define NORTHBRIDGE PCI_DEV(0, 0, 0)
#define NORTHBRIDGE_MMC PCI_DEV(0, 0, 1)
/* The i855 supports max. 2 dual-sided SO-DIMMs. */
#define DIMM_SOCKETS 2 #define DIMM_SOCKETS 2
/* DIMM0 is at 0x50, DIMM1 is at 0x51. */
#define DIMM_SPD_BASE 0x50
struct mem_controller { struct mem_controller {
device_t d0; device_t d0;
uint16_t channel0[DIMM_SOCKETS]; uint16_t channel0[DIMM_SOCKETS];
@ -31,4 +39,4 @@ struct mem_controller {
void sdram_initialize(int controllers, const struct mem_controller *ctrl); void sdram_initialize(int controllers, const struct mem_controller *ctrl);
#endif /* RAMINIT_H */ #endif /* NORTHBRIDGE_INTEL_I855_RAMINIT_H */