mb/google/dedede/var/boxy:Enable wake on USB2/3 (un)plug
Set USB port which corresponds PORTSCN/PORTSCXUSB3 register bits for enable USB wake. BUG=b:302230434 TEST=Verify USB-A device could wake up Boxy Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: I0f6300dc6bbb6fb8226151e49e38f0450b1e71b7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78144 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -82,6 +82,16 @@ chip soc/intel/jasperlake
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register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A1
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register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A1
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register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-C Port C1
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register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-C Port C1
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#Bitmap for Wake Enable on USB attach/detach
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register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \
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USB_PORT_WAKE_ENABLE(2) | \
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USB_PORT_WAKE_ENABLE(3) | \
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USB_PORT_WAKE_ENABLE(4)"
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register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \
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USB_PORT_WAKE_ENABLE(2) | \
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USB_PORT_WAKE_ENABLE(3) | \
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USB_PORT_WAKE_ENABLE(4)"
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device domain 0 on
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device domain 0 on
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device pci 04.0 on
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device pci 04.0 on
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chip drivers/intel/dptf
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chip drivers/intel/dptf
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