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mb/google/dedede/var/boxy:Enable wake on USB2/3 (un)plug 

Set USB port which corresponds PORTSCN/PORTSCXUSB3 register bits for
enable USB wake.

BUG=b:302230434
TEST=Verify USB-A device could wake up Boxy

Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: I0f6300dc6bbb6fb8226151e49e38f0450b1e71b7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78144
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Joey Peng 2023-09-28 14:26:38 +08:00 committed by Felix Held
parent eed9c8322f
commit b6b3c62ea1
1 changed files with 10 additions and 0 deletions
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10
src/mainboard/google/dedede/variants/boxy/overridetree.cb
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@ -82,6 +82,16 @@ chip soc/intel/jasperlake
register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A1
register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-C Port C1
#Bitmap for Wake Enable on USB attach/detach
register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \
USB_PORT_WAKE_ENABLE(2) | \
USB_PORT_WAKE_ENABLE(3) | \
USB_PORT_WAKE_ENABLE(4)"
register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \
USB_PORT_WAKE_ENABLE(2) | \
USB_PORT_WAKE_ENABLE(3) | \
USB_PORT_WAKE_ENABLE(4)"
device domain 0 on
device pci 04.0 on
chip drivers/intel/dptf