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vc/amd/fsp/sabrina/platform_descriptor: update DXIO lane mapping table 

Sabrina only supports PCIe and no SATA or 10 GBit/s ethernet on its DXIO
lanes.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib5aa3abf21e20bbe846f1acfdc2755e97eca1e63
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63121
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Held 2022-03-21 23:54:32 +01:00
parent e102154a5e
commit b6bb0c88be
1 changed files with 7 additions and 16 deletions
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23
src/vendorcode/amd/fsp/sabrina/platform_descriptors.h
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@ -160,29 +160,20 @@ typedef struct __packed {
} fsp_ddi_descriptor; } fsp_ddi_descriptor;
/* /*
* Cezanne DXIO Descriptor: Used for assigning lanes to PCIe/SATA/XGBE engines, * Sabrina DXIO Descriptor: Used for assigning lanes to PCIe engines, configure
* configure bifurcation and other settings. Beware that the lane numbers in * bifurcation and other settings. Beware that the lane numbers in here are the
* here are the logical and not the physical lane numbers! * logical and not the physical lane numbers!
* *
* Cezanne DXIO logical lane to physical PCIe lane mapping: * Sabrina DXIO logical lane to physical PCIe lane mapping:
* *
* logical | FT6 | AM4 * logical | physical
* --------|------------|---------------------- * --------|------------
* [00:03] | GPP[00:03] | GPP[00:03] * [00:03] | GPP[03:00]
* [04:07] | GPP[04:07] | GPP[04:07]/HUB[00:03]
* [08:11] | GPP[08:11] | GFX[15:12]
* [12:15] | n/a | GFX[11:08]
* [16:23] | GFX[00:07] | GFX[07:0]
* *
* Different ports mustn't overlap or be assigned to the same lane(s). Within * Different ports mustn't overlap or be assigned to the same lane(s). Within
* ports with the same width the one with a higher start logical lane number * ports with the same width the one with a higher start logical lane number
* needs to be assigned to a higher PCIe root port number; ports of the same * needs to be assigned to a higher PCIe root port number; ports of the same
* size don't have to be assigned to consecutive PCIe root ports though. * size don't have to be assigned to consecutive PCIe root ports though.
*
* Lanes 2 and 3 can be mapped to the SATA controller on all packages; the FT6
* platform additionally supports mapping lanes 8 and 9 to a SATA controller.
* On embedded SKUs lanes 0 and 1 can be mapped to the Gigabit Ethernet
* controllers.
*/ */
typedef struct __packed { typedef struct __packed {
uint8_t engine_type; // See dxio_engine_type uint8_t engine_type; // See dxio_engine_type