gru: Add watchdog reset support
This patch adds support to reboot the whole board after a hardware watchdog reset, to avoid the usual TPM issues. Work 100% equivalent to Veyron. From my tests it looks like both SRAM and PMUSRAM get preserved across warm reboots. I'm putting the WATCHDOG_TOMBSTONE into PMUSRAM since that makes it easier to deal with in coreboot (PMUSRAM is currently not mapped as cached, so we don't need to worry about flushing the results back before reboot). BRANCH=None BUG=chrome-os-partner:56600 TEST='stop daisydog; cat > /dev/watchdog', press CTRL+D, wait 30 seconds. Confirm that system reboots correctly without entering recovery and we get a HW watchdog event in the eventlog. Change-Id: I317266df40bbb221910017d1a6bdec6a1660a511 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 3b8f3d064ad56d181191c1e1c98a73196cb8d098 Original-Change-Id: I17c5a801bef200d7592a315a955234bca11cf7a3 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/375562 Original-Commit-Queue: Douglas Anderson <dianders@chromium.org> Reviewed-on: https://review.coreboot.org/16578 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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@ -20,6 +20,7 @@ bootblock-y += chromeos.c
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bootblock-y += memlayout.ld
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bootblock-y += pwm_regulator.c
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bootblock-y += boardid.c
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bootblock-y += reset.c
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verstage-y += chromeos.c
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verstage-y += memlayout.ld
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@ -24,6 +24,7 @@
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#include <soc/i2c.h>
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#include <soc/pwm.h>
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#include <soc/spi.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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#include "board.h"
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#include "pwm_regulator.h"
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@ -75,6 +76,9 @@ void bootblock_mainboard_init(void)
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{
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speed_up_boot_cpu();
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if (rkclk_was_watchdog_reset())
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reboot_from_watchdog();
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/* Set pinmux and configure spi flashrom. */
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write32(&rk3399_pmugrf->spi1_rxd, IOMUX_SPI1_RX);
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write32(&rk3399_pmugrf->spi1_csclktx, IOMUX_SPI1_CSCLKTX);
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@ -834,3 +834,9 @@ void rkclk_configure_emmc(void)
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CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT |
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(src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT));
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}
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int rkclk_was_watchdog_reset(void)
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{
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/* Bits 5 and 4 are "second" and "first" global watchdog reset. */
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return read32(&cru_ptr->glb_rst_st) & 0x30;
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}
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@ -112,6 +112,7 @@ void rkclk_configure_spi(unsigned int bus, unsigned int hz);
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void rkclk_configure_tsadc(unsigned int hz);
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void rkclk_configure_vop_aclk(u32 vop_id, u32 aclk_hz);
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void rkclk_ddr_reset(u32 ch, u32 ctl, u32 phy);
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int rkclk_was_watchdog_reset(void);
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uint32_t rkclk_i2c_clock_for_bus(unsigned bus);
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#endif /* __SOC_ROCKCHIP_RK3399_CLOCK_H__ */
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@ -24,6 +24,11 @@ SECTIONS
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DMA_COHERENT(0x10000000, 2M)
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FRAMEBUFFER(0x10200000, 8M)
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/* 8K of special SRAM in PMU power domain. */
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SYMBOL(pmu_sram, 0xFF3B0000)
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WATCHDOG_TOMBSTONE(0xFF3B1FFC, 4)
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SYMBOL(epmu_sram, 0xFF3B2000)
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SRAM_START(0xFF8C0000)
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PRERAM_CBMEM_CONSOLE(0xFF8C0000, 7K)
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TIMESTAMP(0xFF8C1C00, 1K)
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