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soc/intel/meteorlake: Enable GPIO 4 bits pad mode configuration 

This enables SOC_INTEL_COMMON_BLOCK_GPIO_PMODE_4BITS to support 4 bits
GPIO pad mode to configure native function 8 to 15.

BUG=b:239690757
TEST=build and verify pad mode configuration with Meteor Lake mtlrvp

Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Change-Id: Ibf4b13a3d19095d15bf857c7fe4ec0affb54a4e8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66391
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit is contained in:
Jamie Ryu 2022-08-03 01:13:33 -07:00 committed by Martin Roth
parent 4b8092aebb
commit b6c32d7fe4
1 changed files with 1 additions and 0 deletions
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1
src/soc/intel/meteorlake/Kconfig
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@ -56,6 +56,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK_DTT
select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT
select SOC_INTEL_COMMON_BLOCK_GPIO_LOCK_USING_PCR
select SOC_INTEL_COMMON_BLOCK_GPIO_PMODE_4BITS
select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
select SOC_INTEL_COMMON_BLOCK_HDA
select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC if DISABLE_HECI1_AT_PRE_BOOT