intel 82801dx/gx/ix: Commit SMM relocation code to DRAM

Make sure relocation code reaches DRAM before issuing any
SMIs. Snooping and cache coherency may have undefined
behaviour as CPUs do not have uniform MTRR layout yet.

Change-Id: I47a7d684e05ff8c1c2f1f6a5bf8c0bbc561d9eac
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17712
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/southbridge/intel/i82801dx/smi.c

@@ -252,6 +252,7 @@ static void smm_relocate(void)
 	/* copy the SMM relocation code */
 	memcpy((void *)0x38000, &smm_relocation_start,
 			&smm_relocation_end - &smm_relocation_start);
+	wbinvd();
 
 	printk(BIOS_DEBUG, "\n");
 	dump_smi_status(reset_smi_status());

src/southbridge/intel/i82801gx/smi.c

@@ -252,6 +252,7 @@ static void smm_relocate(void)
 	/* copy the SMM relocation code */
 	memcpy((void *)0x38000, &smm_relocation_start,
 			&smm_relocation_end - &smm_relocation_start);
+	wbinvd();
 
 	printk(BIOS_DEBUG, "\n");
 	dump_smi_status(reset_smi_status());

src/southbridge/intel/i82801ix/smi.c

@@ -256,6 +256,7 @@ static void smm_relocate(void)
 	/* copy the SMM relocation code */
 	memcpy((void *)0x38000, &smm_relocation_start,
 			&smm_relocation_end - &smm_relocation_start);
+	wbinvd();
 
 	printk(BIOS_DEBUG, "\n");
 	dump_smi_status(reset_smi_status());