Add support for storing POST codes in CMOS
This will use 3 bytes of CMOS to keep track of the POST code for the current boot while also leaving a record of the previous boot. The active bank is switched early in the bootblock. Test: 1) clear cmos 2) reboot 3) use "mosys nvram dump" to verify that the first byte contains 0x80 and the second byte contains 0xF8 4) powerd_suspend and then resume 5) use "mosys nvram dump" to verify that the first byte contains 0x81 and the second byte contains 0xFD Change-Id: I1ee6bb2dac053018f3042ab5a0b26c435dbfd151 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1743 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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@ -34,3 +34,27 @@ static void sanitize_cmos(void)
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}
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}
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#endif
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#if CONFIG_CMOS_POST
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#include <pc80/mc146818rtc.h>
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static void cmos_post_init(void)
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{
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u8 magic = CMOS_POST_BANK_0_MAGIC;
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/* Switch to the other bank */
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switch (cmos_read(CMOS_POST_BANK_OFFSET)) {
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case CMOS_POST_BANK_1_MAGIC:
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break;
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case CMOS_POST_BANK_0_MAGIC:
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magic = CMOS_POST_BANK_1_MAGIC;
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break;
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default:
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/* Initialize to zero */
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cmos_write(0, CMOS_POST_BANK_0_OFFSET);
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cmos_write(0, CMOS_POST_BANK_1_OFFSET);
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}
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cmos_write(magic, CMOS_POST_BANK_OFFSET);
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}
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#endif
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@ -9,6 +9,9 @@ static void main(unsigned long bist)
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#if CONFIG_USE_OPTION_TABLE
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sanitize_cmos();
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#endif
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#if CONFIG_CMOS_POST
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cmos_post_init();
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#endif
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}
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@ -373,5 +373,23 @@ config CONSOLE_POST
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usually displayed using a so-called "POST card" ISA/PCI/PCI-E
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device) on the debug console.
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config CMOS_POST
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bool "Store post codes in CMOS for debugging"
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depends on !NO_POST
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default n
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help
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If enabled, coreboot will store post codes in CMOS and switch between
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two offsets on each boot so the last post code in the previous boot
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can be retrieved. This uses 3 bytes of CMOS.
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config CMOS_POST_OFFSET
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hex "Offset into CMOS to store POST codes"
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depends on CMOS_POST
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default 0
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help
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If CMOS_POST is enabled then an offset into CMOS must be provided.
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If CONFIG_HAVE_OPTION_TABLE is enabled then it will use the value
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defined in the mainboard option table.
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endmenu
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@ -21,6 +21,7 @@
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#include <arch/io.h>
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#include <console/console.h>
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#include <pc80/mc146818rtc.h>
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/* Write POST information */
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@ -38,6 +39,20 @@ void __attribute__((weak)) mainboard_post(uint8_t value)
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#define mainboard_post(x)
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#endif
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#if CONFIG_CMOS_POST
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static void cmos_post_code(u8 value)
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{
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switch (cmos_read(CMOS_POST_BANK_OFFSET)) {
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case CMOS_POST_BANK_0_MAGIC:
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cmos_write(value, CMOS_POST_BANK_0_OFFSET);
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break;
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case CMOS_POST_BANK_1_MAGIC:
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cmos_write(value, CMOS_POST_BANK_1_OFFSET);
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break;
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}
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}
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#endif /* CONFIG_CMOS_POST */
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void post_code(uint8_t value)
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{
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#if !CONFIG_NO_POST
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@ -45,6 +60,9 @@ void post_code(uint8_t value)
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print_emerg("POST: 0x");
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print_emerg_hex8(value);
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print_emerg("\n");
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#endif
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#if CONFIG_CMOS_POST
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cmos_post_code(value);
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#endif
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outb(value, CONFIG_POST_PORT);
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#endif
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@ -158,4 +158,23 @@ static inline int get_option(void *dest __attribute__((unused)),
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#endif
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#define read_option(name, default) read_option_lowlevel(CMOS_VSTART_ ##name, CMOS_VLEN_ ##name, (default))
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#if CONFIG_CMOS_POST
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#if CONFIG_USE_OPTION_TABLE
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# include "option_table.h"
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# define CMOS_POST_OFFSET (CMOS_VSTART_cmos_post_offset >> 3)
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#else
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# if defined(CONFIG_CMOS_POST_OFFSET)
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# define CMOS_POST_OFFSET CONFIG_CMOS_POST_OFFSET
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# else
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# error "Must define CONFIG_CMOS_POST_OFFSET"
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# endif
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#endif
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#define CMOS_POST_BANK_OFFSET (CMOS_POST_OFFSET)
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#define CMOS_POST_BANK_0_MAGIC 0x80
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#define CMOS_POST_BANK_0_OFFSET (CMOS_POST_OFFSET + 1)
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#define CMOS_POST_BANK_1_MAGIC 0x81
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#define CMOS_POST_BANK_1_OFFSET (CMOS_POST_OFFSET + 2)
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#endif /* CONFIG_CMOS_POST */
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#endif /* PC80_MC146818RTC_H */
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