diff --git a/src/mainboard/intel/coffeelake_rvp/romstage.c b/src/mainboard/intel/coffeelake_rvp/romstage.c
index 2eefccaa2c..475a8155fe 100644
--- a/src/mainboard/intel/coffeelake_rvp/romstage.c
+++ b/src/mainboard/intel/coffeelake_rvp/romstage.c
@@ -27,7 +27,6 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 {
 	FSP_M_CONFIG *mem_cfg;
 	mem_cfg = &mupd->FspmConfig;
-	u8 spd_index;
 
 	mainboard_fill_dq_map_ch0(&mem_cfg->DqByteMapCh0);
 	mainboard_fill_dq_map_ch1(&mem_cfg->DqByteMapCh1);
@@ -36,19 +35,13 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 	mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor);
 	mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget);
 
-	mem_cfg->DqPinsInterleaved = 0;
-	mem_cfg->CaVrefConfig = 0; /* VREF_CA->CHA/CHB */
+	mem_cfg->DqPinsInterleaved = 1;
+	mem_cfg->CaVrefConfig = 2; /* VREF_CA->CHA/CHB */
 	mem_cfg->ECT = 1; /* Early Command Training Enabled */
-	spd_index = 2;
 
-	struct region_device spd_rdev;
-
-	if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0)
-		die("spd.bin not found\n");
-
-	mem_cfg->MemorySpdDataLen = region_device_sz(&spd_rdev);
-	/* Memory leak is ok since we have memory mapped boot media */
-	mem_cfg->MemorySpdPtr00 = (uintptr_t)rdev_mmap_full(&spd_rdev);
-	mem_cfg->RefClk = 0; /* Auto Select CLK freq */
-	mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00;
+	/* Setting standard SPD addresses */
+	mem_cfg->SpdAddressTable[0] = 0xA0;
+	mem_cfg->SpdAddressTable[1] = 0xA2;
+	mem_cfg->SpdAddressTable[2] = 0xA4;
+	mem_cfg->SpdAddressTable[3] = 0xA6;
 }
diff --git a/src/mainboard/intel/coffeelake_rvp/spd/spd_util.c b/src/mainboard/intel/coffeelake_rvp/spd/spd_util.c
index 09bd303aff..73f354d741 100644
--- a/src/mainboard/intel/coffeelake_rvp/spd/spd_util.c
+++ b/src/mainboard/intel/coffeelake_rvp/spd/spd_util.c
@@ -23,8 +23,8 @@ void mainboard_fill_dq_map_ch0(void *dq_map_ptr)
 {
 	/* DQ byte map Ch0 */
 	const u8 dq_map[12] = {
-		0x0F, 0xF0, 0x0F, 0xF0, 0xFF, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
+		0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0,
+		0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 };
 
 	memcpy(dq_map_ptr, dq_map, sizeof(dq_map));
 }
@@ -32,8 +32,8 @@ void mainboard_fill_dq_map_ch0(void *dq_map_ptr)
 void mainboard_fill_dq_map_ch1(void *dq_map_ptr)
 {
 	const u8 dq_map[12] = {
-		0x0F, 0xF0, 0x0F, 0xF0, 0xFF, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
+		0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC,
+		0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 };
 
 	memcpy(dq_map_ptr, dq_map, sizeof(dq_map));
 }
@@ -41,27 +41,17 @@ void mainboard_fill_dq_map_ch1(void *dq_map_ptr)
 void mainboard_fill_dqs_map_ch0(void *dqs_map_ptr)
 {
 	/* DQS CPU<>DRAM map Ch0 */
-	const u8 dqs_map_u[8] = { 0, 3, 2, 1, 5, 6, 7, 4 };
+	const u8 dqs_map_h[8] = { 0, 1, 3, 2, 4, 5, 6, 7 };
 
-	const u8 dqs_map_y[8] = { 2, 0, 3, 1, 6, 5, 7, 4 };
-
-	if (IS_ENABLED(CONFIG_BOARD_INTEL_COFFEELAKE_RVPU))
-		memcpy(dqs_map_ptr, dqs_map_u, sizeof(dqs_map_u));
-	else
-		memcpy(dqs_map_ptr, dqs_map_y, sizeof(dqs_map_y));
+	memcpy(dqs_map_ptr, dqs_map_h, sizeof(dqs_map_h));
 }
 
 void mainboard_fill_dqs_map_ch1(void *dqs_map_ptr)
 {
 	/* DQS CPU<>DRAM map Ch1 */
-	const u8 dqs_map_u[8] = { 3, 0, 1, 2, 5, 6, 4, 7 };
+	const u8 dqs_map_h[8] = { 1, 0, 4, 5, 2, 3, 6, 7 };
 
-	const u8 dqs_map_y[8] = { 3, 1, 2, 0, 4, 5, 6, 7 };
-
-	if (IS_ENABLED(CONFIG_BOARD_INTEL_COFFEELAKE_RVPU))
-		memcpy(dqs_map_ptr, dqs_map_u, sizeof(dqs_map_u));
-	else
-		memcpy(dqs_map_ptr, dqs_map_y, sizeof(dqs_map_y));
+	memcpy(dqs_map_ptr, dqs_map_h, sizeof(dqs_map_h));
 }
 
 void mainboard_fill_rcomp_res_data(void *rcomp_ptr)
@@ -75,7 +65,7 @@ void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr)
 {
 	/* Rcomp target */
 	static const u16 RcompTarget[RCOMP_TARGET_PARAMS] = {
-			80, 40, 40, 40, 30 };
+			100, 33, 32, 33, 28 };
 
 	memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget));
 }