GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

vc/intel/fsp/fsp20/meteorlake: Add VR config entries 

This patch adds UPD entries into the FSP header file to configure VRs
(IA, GT and SA).
- `IccLimit` : VR Fast Vmode ICC Limit support
- `EnableFastVmode` : Enable/Disable VR FastVmode
- `CepEnable` : Enable/Disable CEP (Current Excursion Protection

BUG=b:286809233
TEST=Able to build google/rex.

Change-Id: I477ab7e4c07156759962bd2eab9dff28a0a3f006
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75761
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
This commit is contained in:
Subrata Banik 2023-06-12 16:22:37 +05:30
parent 5da5156ce3
commit b6f45efd64
1 changed files with 74 additions and 46 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

120
src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h
View File

@ -1433,7 +1433,35 @@ typedef struct {
/** Offset 0x06B4 - Reserved
**/
UINT8 Reserved33[336];
UINT8 Reserved33[166];
/** Offset 0x075A - VR Fast Vmode ICC Limit support
Voltage Regulator Fast Vmode ICC Limit. A value of 400 = 100A. A value of 0 corresponds
to feature disabled (no reactive protection). This value represents the current
threshold where the VR would initiate reactive protection if Fast Vmode is enabled.
The value is represented in 1/4 A increments. Range 0-2040. [0] for IA, [1] for
GT, [2] for SA, [3] through [5] are Reserved.
**/
UINT16 IccLimit[6];
/** Offset 0x0766 - Enable/Disable VR FastVmode. The VR will initiate reactive protection if Fast Vmode is enabled.
Enable/Disable VR FastVmode; [0] for IA, [1] for GT, 0: Disable; <b>1: Enable</b>.
[2] for SA, <b>0: Disable</b>; 1: Enable.
0: Disable, 1: Enable
**/
UINT8 EnableFastVmode[6];
/** Offset 0x076C - Enable CEP
Enable/Disable CEP (Current Excursion Protection) Support. [0] for IA, [1] for GT,
0: Disable; <b>1: Enable</b>. [2] for SA, <b>0: Disable</b>; 1: Enable. [3] through
[5] are Reserved.
$EN_DIS
**/
UINT8 CepEnable[6];
/** Offset 0x0772 - Reserved
**/
UINT8 Reserved34[146];
/** Offset 0x0804 - BiosGuard
Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable
@ -1455,7 +1483,7 @@ typedef struct {
/** Offset 0x0807 - Reserved
**/
UINT8 Reserved34;
UINT8 Reserved35;
/** Offset 0x0808 - PrmrrSize
Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable
@ -1469,7 +1497,7 @@ typedef struct {
/** Offset 0x0810 - Reserved
**/
UINT8 Reserved35[8];
UINT8 Reserved36[8];
/** Offset 0x0818 - TxtDprMemoryBase
Enable/Disable. 0: Disable, define default value of TxtDprMemoryBase , 1: enable
@ -1524,7 +1552,7 @@ typedef struct {
/** Offset 0x0849 - Reserved
**/
UINT8 Reserved36[32];
UINT8 Reserved37[32];
/** Offset 0x0869 - Enable PCH HSIO PCIE Rx Set Ctle
Enable PCH PCIe Gen 3 Set CTLE Value.
@ -1711,7 +1739,7 @@ typedef struct {
/** Offset 0x0A85 - Reserved
**/
UINT8 Reserved37;
UINT8 Reserved38;
/** Offset 0x0A86 - SMBUS Base Address
SMBUS Base Address (IO space).
@ -1731,7 +1759,7 @@ typedef struct {
/** Offset 0x0A99 - Reserved
**/
UINT8 Reserved38[16];
UINT8 Reserved39[16];
/** Offset 0x0AA9 - SOC/IOE ClkReq-to-ClkSrc mapping
Number of ClkReq signal assigned to ClkSrc
@ -1740,7 +1768,7 @@ typedef struct {
/** Offset 0x0AB9 - Reserved
**/
UINT8 Reserved39[55];
UINT8 Reserved40[55];
/** Offset 0x0AF0 - Enable PCH PCIE RP Mask
Enable/disable PCH PCIE Root Ports. 0: disable, 1: enable. One bit for each port,
@ -1792,7 +1820,7 @@ typedef struct {
/** Offset 0x0AFE - Reserved
**/
UINT8 Reserved40[2];
UINT8 Reserved41[2];
/** Offset 0x0B00 - DMIC<N> ClkA Pin Muxing (N - DMIC number)
Determines DMIC<N> ClkA Pin muxing. See GPIO_*_MUXING_DMIC<N>_CLKA_*
@ -1812,7 +1840,7 @@ typedef struct {
/** Offset 0x0B11 - Reserved
**/
UINT8 Reserved41[3];
UINT8 Reserved42[3];
/** Offset 0x0B14 - DMIC<N> Data Pin Muxing
Determines DMIC<N> Data Pin muxing. See GPIO_*_MUXING_DMIC<N>_DATA_*
@ -1837,7 +1865,7 @@ typedef struct {
/** Offset 0x0B27 - Reserved
**/
UINT8 Reserved42;
UINT8 Reserved43;
/** Offset 0x0B28 - iDisp-Link T-mode
iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 2: 4T, 3: 8T, 4: 16T
@ -1853,7 +1881,7 @@ typedef struct {
/** Offset 0x0B2A - Reserved
**/
UINT8 Reserved43[6];
UINT8 Reserved44[6];
/** Offset 0x0B30 - CNVi DDR RFI Mitigation
Enable/Disable DDR RFI Mitigation. Default is ENABLE. 0: DISABLE, 1: ENABLE
@ -1863,7 +1891,7 @@ typedef struct {
/** Offset 0x0B31 - Reserved
**/
UINT8 Reserved44[11];
UINT8 Reserved45[11];
/** Offset 0x0B3C - Debug Interfaces
Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub,
@ -1885,7 +1913,7 @@ typedef struct {
/** Offset 0x0B3F - Reserved
**/
UINT8 Reserved45;
UINT8 Reserved46;
/** Offset 0x0B40 - Serial Io Uart Debug BaudRate
Set default BaudRate Supported from 0 - default to 6000000. Recommended values 9600,
@ -1913,7 +1941,7 @@ typedef struct {
/** Offset 0x0B47 - Reserved
**/
UINT8 Reserved46;
UINT8 Reserved47;
/** Offset 0x0B48 - Serial Io Uart Debug Mmio Base
Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdSerialIoUartMode
@ -1929,7 +1957,7 @@ typedef struct {
/** Offset 0x0B4D - Reserved
**/
UINT8 Reserved47;
UINT8 Reserved48;
/** Offset 0x0B4E - Ring PLL voltage offset
Core PLL voltage offset. <b>0: No offset</b>. Range 0-15
@ -1943,7 +1971,7 @@ typedef struct {
/** Offset 0x0B50 - Reserved
**/
UINT8 Reserved48;
UINT8 Reserved49;
/** Offset 0x0B51 - Memory Controller PLL voltage offset
Core PLL voltage offset. <b>0: No offset</b>. Range 0-15
@ -2061,7 +2089,7 @@ typedef struct {
/** Offset 0x0B64 - Reserved
**/
UINT8 Reserved49;
UINT8 Reserved50;
/** Offset 0x0B65 - Write Timing Centering 1D
Enables/Disable Write Timing Centering 1D
@ -2089,7 +2117,7 @@ typedef struct {
/** Offset 0x0B69 - Reserved
**/
UINT8 Reserved50[10];
UINT8 Reserved51[10];
/** Offset 0x0B73 - Read Equalization Training
Enables/Disable Read Equalization Training
@ -2099,7 +2127,7 @@ typedef struct {
/** Offset 0x0B74 - Reserved
**/
UINT8 Reserved51[2];
UINT8 Reserved52[2];
/** Offset 0x0B76 - Write Timing Centering 2D
Enables/Disable Write Timing Centering 2D
@ -2127,7 +2155,7 @@ typedef struct {
/** Offset 0x0B7A - Reserved
**/
UINT8 Reserved52;
UINT8 Reserved53;
/** Offset 0x0B7B - Command Voltage Centering
Enables/Disable Command Voltage Centering
@ -2155,7 +2183,7 @@ typedef struct {
/** Offset 0x0B7F - Reserved
**/
UINT8 Reserved53;
UINT8 Reserved54;
/** Offset 0x0B80 - DIMM SPD Alias Test
Enables/Disable DIMM SPD Alias Test
@ -2171,7 +2199,7 @@ typedef struct {
/** Offset 0x0B82 - Reserved
**/
UINT8 Reserved54;
UINT8 Reserved55;
/** Offset 0x0B83 - Dimm ODT Training
Enables/Disable Dimm ODT Training
@ -2205,7 +2233,7 @@ typedef struct {
/** Offset 0x0B88 - Reserved
**/
UINT8 Reserved55[2];
UINT8 Reserved56[2];
/** Offset 0x0B8A - DIMM CA ODT Training
Enable/Disable DIMM CA ODT Training
@ -2215,7 +2243,7 @@ typedef struct {
/** Offset 0x0B8B - Reserved
**/
UINT8 Reserved56[3];
UINT8 Reserved57[3];
/** Offset 0x0B8E - Read Vref Decap Training
Enable/Disable Read Vref Decap Training
@ -2237,7 +2265,7 @@ typedef struct {
/** Offset 0x0B91 - Reserved
**/
UINT8 Reserved57[4];
UINT8 Reserved58[4];
/** Offset 0x0B95 - Duty Cycle Correction Training
Enable/Disable Duty Cycle Correction Training
@ -2247,7 +2275,7 @@ typedef struct {
/** Offset 0x0B96 - Reserved
**/
UINT8 Reserved58[17];
UINT8 Reserved59[17];
/** Offset 0x0BA7 - ECC Support
Enables/Disable ECC Support
@ -2281,7 +2309,7 @@ typedef struct {
/** Offset 0x0BB3 - Reserved
**/
UINT8 Reserved59;
UINT8 Reserved60;
/** Offset 0x0BB4 - IbeccProtectedRegionBases
IBECC Protected Region Bases per IBECC instance
@ -2361,7 +2389,7 @@ typedef struct {
/** Offset 0x0BEE - Reserved
**/
UINT8 Reserved60;
UINT8 Reserved61;
/** Offset 0x0BEF - Exit On Failure (MRC)
Enables/Disable Exit On Failure (MRC)
@ -2371,7 +2399,7 @@ typedef struct {
/** Offset 0x0BF0 - Reserved
**/
UINT8 Reserved61[4];
UINT8 Reserved62[4];
/** Offset 0x0BF4 - Select if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP
ESelect if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP
@ -2630,7 +2658,7 @@ typedef struct {
/** Offset 0x0C2B - Reserved
**/
UINT8 Reserved62[2];
UINT8 Reserved63[2];
/** Offset 0x0C2D - Rapl Power Floor Ch0
Power budget ,range[255;0],(0= 5.3W Def)
@ -2650,7 +2678,7 @@ typedef struct {
/** Offset 0x0C30 - Reserved
**/
UINT8 Reserved63;
UINT8 Reserved64;
/** Offset 0x0C31 - Energy Performance Gain
Enable/disable Energy Performance Gain. <b>0: Disable</b>; 1: Enable
@ -2660,7 +2688,7 @@ typedef struct {
/** Offset 0x0C32 - Reserved
**/
UINT8 Reserved64;
UINT8 Reserved65;
/** Offset 0x0C33 - User Manual Threshold
Disabled: Predefined threshold will be used.\n
@ -2678,7 +2706,7 @@ typedef struct {
/** Offset 0x0C35 - Reserved
**/
UINT8 Reserved65;
UINT8 Reserved66;
/** Offset 0x0C36 - Power Down Mode
This option controls command bus tristating during idle periods
@ -2715,7 +2743,7 @@ typedef struct {
/** Offset 0x0C3B - Reserved
**/
UINT8 Reserved66[8];
UINT8 Reserved67[8];
/** Offset 0x0C43 - Ask MRC to clear memory content
Ask MRC to clear memory content <b>0: Do not Clear Memory;</b> 1: Clear Memory.
@ -2730,7 +2758,7 @@ typedef struct {
/** Offset 0x0C45 - Reserved
**/
UINT8 Reserved67;
UINT8 Reserved68;
/** Offset 0x0C46 - Post Code Output Port
This option configures Post Code Output Port
@ -2750,7 +2778,7 @@ typedef struct {
/** Offset 0x0C4A - Reserved
**/
UINT8 Reserved68[2];
UINT8 Reserved69[2];
/** Offset 0x0C4C - BCLK RFI Frequency
Bclk RFI Frequency for each SAGV point in Hz units. 98000000Hz = 98MHz <b>0 - No
@ -2793,7 +2821,7 @@ typedef struct {
/** Offset 0x0C62 - Reserved
**/
UINT8 Reserved69[13];
UINT8 Reserved70[13];
/** Offset 0x0C6F - Command Pins Mapping
BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller
@ -2809,7 +2837,7 @@ typedef struct {
/** Offset 0x0C71 - Reserved
**/
UINT8 Reserved70[24];
UINT8 Reserved71[24];
/** Offset 0x0C89 - Skip external display device scanning
Enable: Do not scan for external display device, Disable (Default): Scan external
@ -2845,7 +2873,7 @@ typedef struct {
/** Offset 0x0C8E - Reserved
**/
UINT8 Reserved71[2];
UINT8 Reserved72[2];
/** Offset 0x0C90 - PMR Size
Size of PMR memory buffer. 0x400000 for normal boot and 0x200000 for S3 boot
@ -2859,7 +2887,7 @@ typedef struct {
/** Offset 0x0C95 - Reserved
**/
UINT8 Reserved72[143];
UINT8 Reserved73[143];
/** Offset 0x0D24 - TotalFlashSize
Enable/Disable. 0: Disable, define default value of TotalFlashSize , 1: enable
@ -2875,7 +2903,7 @@ typedef struct {
/** Offset 0x0D28 - Reserved
**/
UINT8 Reserved73[28];
UINT8 Reserved74[28];
/** Offset 0x0D44 - Smbus dynamic power gating
Disable or Enable Smbus dynamic power gating.
@ -2891,7 +2919,7 @@ typedef struct {
/** Offset 0x0D46 - Reserved
**/
UINT8 Reserved74[2];
UINT8 Reserved75[2];
/** Offset 0x0D48 - SMBUS SPD Write Disable
Set/Clear Smbus SPD Write Disable. 0: leave SPD Write Disable bit; 1: set SPD Write
@ -2902,7 +2930,7 @@ typedef struct {
/** Offset 0x0D49 - Reserved
**/
UINT8 Reserved75[34];
UINT8 Reserved76[34];
/** Offset 0x0D6B - HECI Timeouts
0: Disable, 1: Enable (Default) timeout check for HECI
@ -2955,7 +2983,7 @@ typedef struct {
/** Offset 0x0D73 - Reserved
**/
UINT8 Reserved76[100];
UINT8 Reserved77[100];
/** Offset 0x0DD7 - Avx2 Voltage Guardband Scaling Factor
AVX2 Voltage Guardband Scale factor applied to AVX2 workloads. Range is 0-200 in
@ -2978,7 +3006,7 @@ typedef struct {
/** Offset 0x0DDA - Reserved
**/
UINT8 Reserved77[2];
UINT8 Reserved78[2];
/** Offset 0x0DDC - SerialIoUartDebugRxPinMux - FSPM
Select RX pin muxing for SerialIo UART used for debug
@ -3004,7 +3032,7 @@ typedef struct {
/** Offset 0x0DEC - Reserved
**/
UINT8 Reserved78[188];
UINT8 Reserved79[188];
} FSP_M_CONFIG;
/** Fsp M UPD Configuration