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northbridge/amd/amdmct: Fix burst write depth on K10 rev. D and later 

The BKDG for K10 revision D and later processors recommends a smaller
MCT burst write queue depth when using unganged memory.

TEST: Booted ASUS KFSN4-DRE with both Opteron 8356 and Opteron 2431
processors.

Change-Id: I36718d4972c9d2d0bdd3274191503b5fcd803f15
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8500
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Timothy Pearson 2015-02-20 13:13:35 -06:00 committed by Kyösti Mälkki
parent 982473536b
commit b6fa61a121
1 changed files with 7 additions and 1 deletions
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8
src/northbridge/amd/amdmct/mct/mct_d.c
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@ -1,6 +1,7 @@
/* /*
* This file is part of the coreboot project. * This file is part of the coreboot project.
* *
* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
* Copyright (C) 2007-2008 Advanced Micro Devices, Inc. * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
@ -749,7 +750,12 @@ static void DCTMemClr_Sync_D(struct MCTStatStruc *pMCTstat,
} while (!(val & (1 << Dr_MemClrStatus))); } while (!(val & (1 << Dr_MemClrStatus)));
} }
val = 0x0FE40FC0; // BKDG recommended /* Implement BKDG Rev 3.62 recommendations */
val = 0x0FE40F80;
if (!(mctGetLogicalCPUID(0) & AMD_FAM10_LT_D) && mctGet_NVbits(NV_Unganged))
val |= (0x18 << 2);
else
val |= (0x10 << 2);
val |= MCCH_FlushWrOnStpGnt; // Set for S3 val |= MCCH_FlushWrOnStpGnt; // Set for S3
Set_NB32(dev, 0x11C, val); Set_NB32(dev, 0x11C, val);
} }