mb/google/hatch: Enable touch panel support
Following changes are done to enable touch screen support on hatch 1. Enable I2C1 device at 400Khz at 3.3V 2. Configure GPIO for touch screen 3. Add ACPI entry for ELAN touch panel 4. update GPIO table with not connected GPIO pins for panel BUG=b:120914069 BRANCH=none TEST=check if code compiles with changes. Change-Id: I8dab07dad4cb197865bb9cf0e8da240810fcfabe Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/30425 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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@ -25,6 +25,7 @@ chip soc/intel/cannonlake
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#| | for TPM communication |
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#| | for TPM communication |
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#| | before memory is up |
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#| | before memory is up |
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#| I2C0 | Touchpad |
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#| I2C0 | Touchpad |
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#| I2C1 | Touch screen |
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#+-------------------+---------------------------+
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#+-------------------+---------------------------+
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register "common_soc_config" = "{
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register "common_soc_config" = "{
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.gspi[0] = {
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.gspi[0] = {
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@ -34,6 +35,9 @@ chip soc/intel/cannonlake
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.i2c[0] = {
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.i2c[0] = {
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.speed = I2C_SPEED_FAST,
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.speed = I2C_SPEED_FAST,
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},
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},
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.i2c[1] = {
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.speed = I2C_SPEED_FAST,
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},
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}"
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}"
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# FSP configuration
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# FSP configuration
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@ -167,7 +171,21 @@ chip soc/intel/cannonlake
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device i2c 15 on end
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device i2c 15 on end
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end
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end
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end # I2C #0
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end # I2C #0
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device pci 15.1 off end # I2C #1
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device pci 15.1 on
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chip drivers/i2c/generic
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register "hid" = ""ELAN0001""
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register "desc" = ""ELAN Touchscreen""
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register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)"
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register "probed" = "1"
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register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)"
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register "reset_delay_ms" = "100"
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register "reset_off_delay_ms" = "5"
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register "has_power_resource" = "1"
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register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C4)"
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register "stop_off_delay_ms" = "5"
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device i2c 49 on end
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end
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end # I2C #1
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device pci 15.2 off end # I2C #2
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device pci 15.2 off end # I2C #2
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device pci 15.3 off end # I2C #3
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device pci 15.3 off end # I2C #3
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device pci 16.0 on end # Management Engine Interface 1
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device pci 16.0 on end # Management Engine Interface 1
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@ -31,6 +31,8 @@ static const struct pad_config gpio_table[] = {
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PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
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/* H1_SLAVE_SPI_MOSI_R */
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/* H1_SLAVE_SPI_MOSI_R */
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PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
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/* TOUCHSCREEN_DIS_L */
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PAD_CFG_GPO(GPP_C4, 0, DEEP),
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/* GPP_C11_TP => NC */
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/* GPP_C11_TP => NC */
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PAD_NC(GPP_C11, DN_20K),
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PAD_NC(GPP_C11, DN_20K),
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/* GPP_C10_TP => NC */
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/* GPP_C10_TP => NC */
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@ -39,12 +41,20 @@ static const struct pad_config gpio_table[] = {
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PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
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/* PCH_I2C_TRACKPAD_SCL */
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/* PCH_I2C_TRACKPAD_SCL */
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PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
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/* H1_PCH_INT_ODL */
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/* PCH_I2C_TOUCHSCREEN_SDA */
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PAD_CFG_GPI_APIC(GPP_C21, NONE, DEEP, LEVEL, INVERT),
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PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
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/* PCH_I2C_TOUCHSCREEN_SCL */
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PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
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/* PCH_WP_OD */
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/* PCH_WP_OD */
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PAD_CFG_GPI(GPP_C20, NONE, DEEP),
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PAD_CFG_GPI(GPP_C20, NONE, DEEP),
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/* H1_PCH_INT_ODL */
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PAD_CFG_GPI_APIC(GPP_C21, NONE, DEEP, LEVEL, INVERT),
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/* EC_IN_RW_OD */
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/* EC_IN_RW_OD */
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PAD_CFG_GPI(GPP_C22, NONE, DEEP),
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PAD_CFG_GPI(GPP_C22, NONE, DEEP),
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/* TOUCHSCREEN_RST_L */
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PAD_CFG_GPO(GPP_D15, 0, DEEP),
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/* TOUCHSCREEN_INT_L */
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PAD_CFG_GPI_APIC(GPP_D16, NONE, DEEP, LEVEL, INVERT),
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/* SATAGP1 */
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/* SATAGP1 */
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PAD_CFG_NF(GPP_E1, NONE, DEEP, NF2),
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PAD_CFG_NF(GPP_E1, NONE, DEEP, NF2),
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/* M2_SSD_PE_WAKE_ODL */
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/* M2_SSD_PE_WAKE_ODL */
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