soc/mediatek/mt8188: Add GPIO driving functions
Add GPIO driving functions to adjust pin driving. This implementation is according to chapter 5.2 in MT8188 Functional Specification. BUG=b:270911452 TEST=build pass Change-Id: I87cb8dc00c90fd5b3c0b8bdf5acb92b6f7393a73 Signed-off-by: Jason Chen <Jason-ch.Chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74063 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Jason Chen
Rex-BC Chen
parent
61aac5b73f
commit
b7089e98e7
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@ -8,6 +8,227 @@
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#include <device/mmio.h>
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#include <gpio.h>
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#define SPI_AP_GPIO_BASE 125
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enum {
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SPI_AP_CLK_ROM = 0,
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SPI_AP_CS_ROM_L = 1,
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SPI_AP_DO_ROM_DI = 2,
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SPI_AP_DI_ROM_DO = 3,
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};
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static const struct gpio_drv_info bootblock_gpio_driving_info[] = {
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[SPI_AP_CLK_ROM] = { 0x20, 24, 3, },
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[SPI_AP_CS_ROM_L] = { 0x20, 24, 3, },
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[SPI_AP_DO_ROM_DI] = { 0x20, 24, 3, },
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[SPI_AP_DI_ROM_DO] = { 0x20, 27, 3, },
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};
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static const struct gpio_drv_info gpio_driving_info[] = {
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[0] = { 0x00, 24, 3, },
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[1] = { 0x00, 27, 3, },
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[2] = { 0x10, 0, 3, },
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[3] = { 0x10, 3, 3, },
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[4] = { 0x20, 9, 3, },
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[5] = { 0x20, 9, 3, },
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[6] = { 0x20, 9, 3, },
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[7] = { 0x10, 6, 3, },
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[8] = { 0x10, 9, 3, },
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[9] = { 0x10, 12, 3, },
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[10] = { 0x10, 15, 3, },
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[11] = { 0x20, 12, 3, },
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[12] = { 0x10, 24, 3, },
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[13] = { 0x10, 27, 3, },
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[14] = { 0x20, 0, 3, },
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[15] = { 0x20, 3, 3, },
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[16] = { 0x10, 15, 3, },
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[17] = { 0x10, 15, 3, },
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[18] = { 0x00, 27, 3, },
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[19] = { 0x00, 27, 3, },
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[20] = { 0x00, 27, 3, },
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[21] = { 0x00, 27, 3, },
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[22] = { 0x00, 0, 3, },
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[23] = { 0x00, 3, 3, },
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[24] = { 0x00, 6, 3, },
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[25] = { 0x20, 6, 3, },
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[26] = { 0x20, 6, 3, },
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[27] = { 0x20, 6, 3, },
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[28] = { 0x20, 9, 3, },
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[29] = { 0x20, 3, 3, },
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[30] = { 0x20, 6, 3, },
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[31] = { 0x20, 12, 3, },
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[32] = { 0x20, 12, 3, },
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[33] = { 0x20, 15, 3, },
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[34] = { 0x20, 15, 3, },
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[35] = { 0x20, 12, 3, },
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[36] = { 0x20, 15, 3, },
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[37] = { 0x10, 27, 3, },
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[38] = { 0x10, 18, 3, },
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[39] = { 0x10, 21, 3, },
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[40] = { 0x10, 24, 3, },
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[41] = { 0x20, 0, 3, },
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[42] = { 0x20, 18, 3, },
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[43] = { 0x20, 18, 3, },
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[44] = { 0x20, 18, 3, },
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[45] = { 0x20, 21, 3, },
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[46] = { 0x10, 15, 3, },
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[47] = { 0x20, 3, 3, },
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[48] = { 0x20, 3, 3, },
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[49] = { 0x20, 3, 3, },
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[50] = { 0x00, 6, 3, },
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[51] = { 0x00, 3, 3, },
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[52] = { 0x00, 0, 3, },
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[53] = { 0x00, 9, 3, },
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[54] = { 0x00, 12, 3, },
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[55] = { 0x20, 27, 3, },
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[56] = { 0x30, 6, 3, },
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[57] = { 0x30, 9, 3, },
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[58] = { 0x30, 15, 3, },
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[59] = { 0x30, 0, 3, },
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[60] = { 0x30, 9, 3, },
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[61] = { 0x30, 3, 3, },
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[62] = { 0x30, 12, 3, },
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[63] = { 0x30, 12, 3, },
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[64] = { 0x30, 18, 3, },
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[65] = { 0x10, 0, 3, },
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[66] = { 0x10, 6, 3, },
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[67] = { 0x10, 3, 3, },
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[68] = { 0x10, 9, 3, },
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[69] = { 0x30, 18, 3, },
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[70] = { 0x30, 15, 3, },
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[71] = { 0x40, 0, 3, },
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[72] = { 0x30, 27, 3, },
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[73] = { 0x30, 21, 3, },
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[74] = { 0x30, 24, 3, },
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[75] = { 0x40, 6, 3, },
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[76] = { 0x40, 3, 3, },
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[77] = { 0x40, 12, 3, },
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[78] = { 0x40, 9, 3, },
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[79] = { 0x10, 15, 3, },
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[80] = { 0x10, 12, 3, },
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[81] = { 0x10, 21, 3, },
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[82] = { 0x10, 18, 3, },
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[83] = { 0x30, 0, 3, },
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[84] = { 0x20, 27, 3, },
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[85] = { 0x30, 0, 3, },
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[86] = { 0x20, 6, 3, },
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[87] = { 0x20, 6, 3, },
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[88] = { 0x20, 6, 3, },
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[89] = { 0x20, 6, 3, },
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[90] = { 0x30, 0, 3, },
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[91] = { 0x30, 0, 3, },
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[92] = { 0x20, 9, 3, },
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[93] = { 0x20, 9, 3, },
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[94] = { 0x20, 9, 3, },
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[95] = { 0x20, 9, 3, },
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[96] = { 0x20, 21, 3, },
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[97] = { 0x20, 21, 3, },
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[98] = { 0x20, 24, 3, },
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[99] = { 0x20, 21, 3, },
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[100] = { 0x30, 6, 3, },
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[101] = { 0x00, 0, 3, },
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[102] = { 0x00, 15, 3, },
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[103] = { 0x00, 9, 3, },
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[104] = { 0x00, 12, 3, },
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[105] = { 0x00, 3, 3, },
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[106] = { 0x00, 6, 3, },
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[107] = { 0x20, 6, 3, },
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[108] = { 0x20, 6, 3, },
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[109] = { 0x20, 6, 3, },
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[110] = { 0x20, 6, 3, },
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[111] = { 0x20, 15, 3, },
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[112] = { 0x20, 15, 3, },
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[113] = { 0x20, 15, 3, },
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[114] = { 0x20, 12, 3, },
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[115] = { 0x20, 12, 3, },
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[116] = { 0x20, 12, 3, },
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[117] = { 0x20, 12, 3, },
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[118] = { 0x20, 12, 3, },
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[119] = { 0x20, 15, 3, },
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[120] = { 0x20, 18, 3, },
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[121] = { 0x10, 3, 3, },
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[122] = { 0x10, 12, 3, },
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[123] = { 0x10, 9, 3, },
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[124] = { 0x10, 6, 3, },
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[125] = { 0x20, 24, 3, },
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[126] = { 0x20, 24, 3, },
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[127] = { 0x20, 24, 3, },
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[128] = { 0x20, 27, 3, },
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[129] = { 0x20, 27, 3, },
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[130] = { 0x20, 27, 3, },
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[131] = { 0x00, 0, 3, },
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[132] = { 0x00, 15, 3, },
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[133] = { 0x00, 18, 3, },
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[134] = { 0x00, 21, 3, },
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[135] = { 0x20, 15, 3, },
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[136] = { 0x20, 18, 3, },
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[137] = { 0x20, 18, 3, },
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[138] = { 0x20, 18, 3, },
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[139] = { 0x20, 18, 3, },
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[140] = { 0x20, 21, 3, },
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[141] = { 0x20, 21, 3, },
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[142] = { 0x20, 21, 3, },
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[143] = { 0x00, 3, 3, },
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[144] = { 0x00, 6, 3, },
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[145] = { 0x00, 9, 3, },
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[146] = { 0x00, 12, 3, },
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[147] = { 0x20, 21, 3, },
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[148] = { 0x20, 24, 3, },
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[149] = { 0x20, 24, 3, },
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[150] = { 0x20, 24, 3, },
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[151] = { 0x10, 15, 3, },
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[152] = { 0x10, 12, 3, },
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[153] = { 0x10, 9, 3, },
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[154] = { 0x10, 6, 3, },
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[155] = { 0x10, 21, 3, },
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[156] = { 0x00, 21, 3, },
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[157] = { 0x00, 18, 3, },
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[158] = { 0x10, 3, 3, },
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[159] = { 0x10, 0, 3, },
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[160] = { 0x00, 27, 3, },
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[161] = { 0x00, 24, 3, },
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[162] = { 0x10, 18, 3, },
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[163] = { 0x00, 12, 3, },
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[164] = { 0x00, 9, 3, },
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[165] = { 0x00, 15, 3, },
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[166] = { 0x00, 18, 3, },
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[167] = { 0x00, 21, 3, },
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[168] = { 0x00, 24, 3, },
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[169] = { 0x00, 18, 3, },
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[170] = { 0x00, 15, 3, },
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[171] = { 0x00, 21, 3, },
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[172] = { 0x00, 24, 3, },
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[173] = { 0x00, 27, 3, },
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[174] = { 0x10, 0, 3, },
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[175] = { 0x30, 3, 3, },
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[176] = { 0x30, 3, 3, },
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};
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_Static_assert(ARRAY_SIZE(gpio_driving_info) == GPIO_NUM,
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"gpio_driving_info array size not match");
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/* Unimplemented GPIOs are intentionally omitted here with width=0 */
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static const struct gpio_drv_info gpio_driving_adv_info[] = {
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[53] = { 0x20, 0, 3, },
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[54] = { 0x20, 3, 3, },
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[55] = { 0x60, 0, 3, },
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[56] = { 0x60, 9, 3, },
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[57] = { 0x50, 0, 3, },
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[58] = { 0x50, 6, 3, },
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[59] = { 0x60, 3, 3, },
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[60] = { 0x60, 12, 3, },
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[61] = { 0x60, 6, 3, },
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[62] = { 0x60, 15, 3, },
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[63] = { 0x50, 3, 3, },
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[64] = { 0x50, 9, 3, },
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[65] = { 0x30, 0, 3, },
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[66] = { 0x30, 6, 3, },
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[67] = { 0x30, 3, 3, },
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[68] = { 0x30, 9, 3, },
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[175] = { 0x50, 12, 3, },
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[176] = { 0x50, 15, 3, },
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};
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void *gpio_find_reg_addr(gpio_t gpio)
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{
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void *reg_addr;
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@ -31,3 +252,29 @@ void *gpio_find_reg_addr(gpio_t gpio)
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return reg_addr;
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}
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const struct gpio_drv_info *get_gpio_driving_info(uint32_t raw_id)
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{
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if (ENV_BOOTBLOCK) {
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uint32_t id = raw_id - SPI_AP_GPIO_BASE;
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if (id >= ARRAY_SIZE(bootblock_gpio_driving_info))
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return NULL;
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return &bootblock_gpio_driving_info[id];
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} else {
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if (raw_id >= ARRAY_SIZE(gpio_driving_info))
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return NULL;
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return &gpio_driving_info[raw_id];
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}
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}
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const struct gpio_drv_info *get_gpio_driving_adv_info(uint32_t raw_id)
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{
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if (ENV_BOOTBLOCK) {
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return NULL;
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} else {
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if (raw_id >= ARRAY_SIZE(gpio_driving_adv_info))
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return NULL;
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return &gpio_driving_adv_info[raw_id];
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}
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}
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