Add support for the Mitac 6513WU mainboard, a Compaq OEM board using the
i810 chipset. Not all hardware has been tested, but my test PC boots Linux (via FILO) without any problems. Also: Add support for the SMSC LPC47U33X to the generic 'smscsuperio' driver. Signed-off-by: Michael Gold <mgold@ncf.ca> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4401 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Michael Gold
Uwe Hermann
parent
3f1458ddd4
commit
b70a45afd0
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2009 Michael Gold <mgold@ncf.ca>
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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## CONFIG_XIP_ROM_SIZE must be a power of 2.
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default CONFIG_XIP_ROM_SIZE = 64 * 1024
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include /config/nofailovercalculation.lb
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arch i386 end
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driver mainboard.o
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if CONFIG_HAVE_PIRQ_TABLE
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object irq_tables.o
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end
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makerule ./failover.E
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depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
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action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
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end
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makerule ./failover.inc
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depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
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action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
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end
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makerule ./auto.E
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# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
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depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
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# Note: The -mcpu=p2 is important, or else... 'too few registers'.
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action "../romcc -mcpu=p2 -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
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end
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makerule ./auto.inc
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# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
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depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
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# Note: The -mcpu=p2 is important, or else... 'too few registers'.
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action "../romcc -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
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end
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mainboardinit cpu/x86/16bit/entry16.inc
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mainboardinit cpu/x86/32bit/entry32.inc
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ldscript /cpu/x86/16bit/entry16.lds
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ldscript /cpu/x86/32bit/entry32.lds
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if CONFIG_USE_FALLBACK_IMAGE
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mainboardinit cpu/x86/16bit/reset16.inc
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ldscript /cpu/x86/16bit/reset16.lds
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else
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mainboardinit cpu/x86/32bit/reset32.inc
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ldscript /cpu/x86/32bit/reset32.lds
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end
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mainboardinit arch/i386/lib/cpu_reset.inc
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mainboardinit arch/i386/lib/id.inc
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ldscript /arch/i386/lib/id.lds
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if CONFIG_USE_FALLBACK_IMAGE
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ldscript /arch/i386/lib/failover.lds
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mainboardinit ./failover.inc
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end
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mainboardinit cpu/x86/fpu/enable_fpu.inc
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mainboardinit cpu/x86/mmx/enable_mmx.inc
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mainboardinit ./auto.inc
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mainboardinit cpu/x86/mmx/disable_mmx.inc
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dir /pc80
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config chip.h
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chip northbridge/intel/i82810 # Northbridge
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device apic_cluster 0 on # APIC cluster
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chip cpu/intel/socket_PGA370 # CPU
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device apic 0 on end # APIC
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end
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end
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device pci_domain 0 on # PCI domain
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device pci 0.0 on end # Graphics Memory Controller Hub (GMCH)
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chip drivers/pci/onboard
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device pci 1.0 on end
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register "rom_address" = "0xfff80000" # 512 KB image
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end
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chip southbridge/intel/i82801xx # Southbridge
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register "pirqa_routing" = "0x03"
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register "pirqb_routing" = "0x05"
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register "pirqc_routing" = "0x09"
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register "pirqd_routing" = "0x0b"
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register "ide0_enable" = "1"
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register "ide1_enable" = "1"
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device pci 1e.0 on # PCI bridge
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device pci 5.0 on end # Audio controller (ESS ES1988)
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end
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device pci 1f.0 on # ISA bridge
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chip superio/smsc/smscsuperio # Super I/O (SMSC LPC47U332)
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device pnp 4e.0 on # Floppy
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io 0x60 = 0x3f0
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irq 0x70 = 6
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drq 0x74 = 2
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end
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device pnp 4e.3 on # Parallel port
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io 0x60 = 0x378
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irq 0x70 = 7
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drq 0x74 = 3
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end
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device pnp 4e.4 on # COM1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 4e.5 on # MIDI port (MPU-401)
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io 0x60 = 0x330
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irq 0x70 = 10
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end
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device pnp 4e.7 on # PS/2 keyboard / mouse
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io 0x60 = 0x60 # XXX: not relocatable
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io 0x62 = 0x64 # XXX: not relocatable
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irq 0x70 = 1 # PS/2 keyboard interrupt
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irq 0x72 = 12 # PS/2 mouse interrupt
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end
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device pnp 4e.9 on # Game port
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io 0x60 = 0x201
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end
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device pnp 4e.a on # Runtime registers
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io 0x60 = 0x400
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end
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device pnp 4e.b off end # SMBus
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end
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end
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device pci 1f.1 on end # IDE
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device pci 1f.2 on end # USB
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device pci 1f.3 on end # SMbus
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device pci 1f.5 off end # Audio controller
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device pci 1f.6 off end # Modem
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end
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end
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end
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@ -0,0 +1,110 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2009 Michael Gold <mgold@ncf.ca>
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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uses CC
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uses CONFIG_CBFS
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uses CONFIG_COMPRESSED_PAYLOAD_LZMA
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uses CONFIG_CONSOLE_SERIAL8250
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uses CONFIG_CONSOLE_VGA
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uses CONFIG_CROSS_COMPILE
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uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
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uses CONFIG_FALLBACK_SIZE
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uses CONFIG_HAVE_FALLBACK_BOOT
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uses CONFIG_HAVE_HARD_RESET
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uses CONFIG_HAVE_MP_TABLE
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uses CONFIG_HAVE_OPTION_TABLE
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uses CONFIG_HAVE_PIRQ_TABLE
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uses CONFIG_HEAP_SIZE
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uses CONFIG_IRQ_SLOT_COUNT
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uses CONFIG_MAINBOARD
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uses CONFIG_MAINBOARD_PART_NUMBER
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uses CONFIG_MAINBOARD_VENDOR
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uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
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uses CONFIG_OBJCOPY
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uses CONFIG_PAYLOAD_SIZE
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uses CONFIG_PCI_ROM_RUN
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uses CONFIG_RAMBASE
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uses CONFIG_ROMBASE
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uses CONFIG_ROM_IMAGE_SIZE
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uses CONFIG_ROM_PAYLOAD
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uses CONFIG_ROM_PAYLOAD_START
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uses CONFIG_ROM_SECTION_OFFSET
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uses CONFIG_ROM_SECTION_SIZE
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uses CONFIG_ROM_SIZE
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uses CONFIG_STACK_SIZE
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uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
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uses CONFIG_TTYS0_BASE
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uses CONFIG_TTYS0_BAUD
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uses CONFIG_TTYS0_LCS
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uses CONFIG_UDELAY_TSC
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uses CONFIG_USE_FALLBACK_IMAGE
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uses CONFIG_USE_INIT
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uses CONFIG_USE_OPTION_TABLE
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uses CONFIG_XIP_ROM_BASE
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uses CONFIG_XIP_ROM_SIZE
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uses COREBOOT_EXTRA_VERSION
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uses HOSTCC
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# Motherboard info, tables, etc.
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default CONFIG_MAINBOARD_VENDOR = "Mitac"
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default CONFIG_MAINBOARD_PART_NUMBER = "6513WU"
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default CONFIG_IRQ_SLOT_COUNT = 8
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default CONFIG_HAVE_PIRQ_TABLE = 1
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default CONFIG_HAVE_MP_TABLE = 0
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default CONFIG_HAVE_OPTION_TABLE = 0
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default CONFIG_USE_OPTION_TABLE = 0
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# ROM layout
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default CONFIG_ROM_SIZE = 512 * 1024
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default CONFIG_ROM_IMAGE_SIZE = 128 * 1024
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default CONFIG_FALLBACK_SIZE = 256 * 1024
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default CONFIG_HAVE_FALLBACK_BOOT = 1
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default CONFIG_ROM_PAYLOAD = 1
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default CONFIG_CBFS = 0
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# RAM layout
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default CONFIG_RAMBASE = 0x00004000
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default CONFIG_STACK_SIZE = 8 * 1024
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default CONFIG_HEAP_SIZE = 16 * 1024
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# Misc. settings
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default CONFIG_USE_INIT = 0
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default CONFIG_HAVE_HARD_RESET = 0
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default CONFIG_UDELAY_TSC = 1
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default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
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# Compiler setup
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default CONFIG_CROSS_COMPILE = ""
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default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
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default HOSTCC = "gcc"
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# Console settings
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default CONFIG_CONSOLE_SERIAL8250 = 1
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default CONFIG_TTYS0_BAUD = 115200
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default CONFIG_TTYS0_BASE = 0x3f8
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default CONFIG_TTYS0_LCS = 0x3 # 8n1
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default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 7 # No debugging/spew
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default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
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# Enable onboard video
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default CONFIG_CONSOLE_VGA = 1
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default CONFIG_PCI_ROM_RUN = 1
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end
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@ -0,0 +1,68 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2009 Michael Gold <mgold@ncf.ca>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#define ASSEMBLY 1
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#include <stdint.h>
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#include <stdlib.h>
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#include <device/pci_def.h>
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#include <arch/io.h>
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#include <device/pnp_def.h>
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#include <arch/romcc_io.h>
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#include <arch/hlt.h>
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#include "pc80/serial.c"
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#include "arch/i386/lib/console.c"
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#include "ram/ramtest.c"
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#include "southbridge/intel/i82801xx/i82801xx_early_smbus.c"
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#include "northbridge/intel/i82810/raminit.h"
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#include "lib/debug.c"
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#include "pc80/udelay_io.c"
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#include "lib/delay.c"
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#include "cpu/x86/mtrr/earlymtrr.c"
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#include "cpu/x86/bist.h"
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#include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"
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#define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1)
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static inline int spd_read_byte(unsigned int device, unsigned int address)
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{
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return smbus_read_byte(device, address);
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}
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#include "northbridge/intel/i82810/raminit.c"
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/* #include "northbridge/intel/i82810/debug.c" */
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static void main(unsigned long bist)
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{
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if (bist == 0)
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early_mtrr_init();
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smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
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uart_init();
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console_init();
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report_bist_failure(bist);
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enable_smbus();
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/* dump_spd_registers(); */
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sdram_set_registers();
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sdram_set_spd_registers();
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sdram_enable();
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/* ram_check(0, 640 * 1024); */
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}
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2009 Michael Gold <mgold@ncf.ca>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
|
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* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
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*
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* This program is distributed in the hope that it will be useful,
|
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
|
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*
|
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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extern struct chip_operations mainboard_ops;
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struct mainboard_config {};
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@ -0,0 +1,63 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2009 Michael Gold <mgold@ncf.ca>
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*
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* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
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*
|
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* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <arch/pirq_routing.h>
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/*
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* Each of PIRQA..D can be routed to IRQ 3-7, 9-12, 14, or 15; but the
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* selected IRQs can't be shared with ISA devices (Intel DS 290655-003,
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* section 5.7.6).
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*
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* Correspondingly, the IRQs used on the Super I/O (4,6,7,10,12) are
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* excluded from the masks, leaving 0xca28 (3,5,9,11,14,15).
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*/
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const struct irq_routing_table intel_irq_routing_table = {
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PIRQ_SIGNATURE, /* u32 signature */
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PIRQ_VERSION, /* u16 version */
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32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
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0x00, /* Interrupt router bus */
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(0x1f << 3) | 0x0, /* Interrupt router dev */
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0, /* IRQs devoted exclusively to PCI usage */
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0x8086, /* Vendor */
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0x7000, /* Device */
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0, /* Miniport */
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
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0xb6, /* Checksum (has to be set to some value that
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* would give 0 after the sum of all bytes
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* for this structure (including checksum).
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*/
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{
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/* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
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{0x00, (0x1f << 3) | 0x0, {{0x00, 0x0000}, {0x61, 0xca28}, {0x00, 0x0000}, {0x63, 0xca28}}, 0x0, 0x0},
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{0x00, (0x1e << 3) | 0x0, {{0x60, 0xca28}, {0x61, 0xca28}, {0x62, 0xca28}, {0x63, 0xca28}}, 0x0, 0x0},
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{0x00, (0x01 << 3) | 0x0, {{0x60, 0xca28}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
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{0x01, (0x05 << 3) | 0x0, {{0x63, 0xca28}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
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{0x01, (0x08 << 3) | 0x0, {{0x60, 0xca28}, {0x61, 0xca28}, {0x62, 0xca28}, {0x63, 0xca28}}, 0x1, 0x0},
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{0x01, (0x09 << 3) | 0x0, {{0x61, 0xca28}, {0x62, 0xca28}, {0x63, 0xca28}, {0x60, 0xca28}}, 0x2, 0x0},
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{0x01, (0x0a << 3) | 0x0, {{0x62, 0xca28}, {0x63, 0xca28}, {0x60, 0xca28}, {0x61, 0xca28}}, 0x3, 0x0},
|
||||
{0x01, (0x0b << 3) | 0x0, {{0x63, 0xca28}, {0x60, 0xca28}, {0x61, 0xca28}, {0x62, 0xca28}}, 0x4, 0x0},
|
||||
}
|
||||
};
|
||||
|
||||
unsigned long write_pirq_routing_table(unsigned long addr)
|
||||
{
|
||||
return copy_pirq_routing_table(addr);
|
||||
}
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2009 Michael Gold <mgold@ncf.ca>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <device/device.h>
|
||||
#include "chip.h"
|
||||
|
||||
struct chip_operations mainboard_ops = {
|
||||
CHIP_NAME("Mitac 6513WU Mainboard")
|
||||
};
|
||||
|
|
@ -51,6 +51,7 @@
|
|||
#define FDC37M81X 0x4d
|
||||
#define FDC37M60X 0x47
|
||||
#define LPC47B27X 0x51 /* a.k.a. LPC47B272 */
|
||||
#define LPC47U33X 0x54
|
||||
#define LPC47M10X 0x59 /* Same ID: LPC47M112, LPC47M13X */
|
||||
#define LPC47M15X 0x60 /* Same ID: LPC47M192 */
|
||||
#define LPC47S45X 0x62
|
||||
|
|
@ -129,6 +130,7 @@ static const struct logical_devices {
|
|||
{LPC47M15X,{0, 3, 4, 5, -1, 7, -1, -1, -1, 9, 10, 11, -1, -1, -1}},
|
||||
{LPC47S45X,{0, 3, 4, 5, 6, 7, -1, 8, -1, -1, -1, -1, 10, -1, 11}},
|
||||
{LPC47B397,{0, 3, 4, 5, -1, 7, -1, -1, 8, -1, -1, -1, 10, -1, -1}},
|
||||
{LPC47U33X,{0, 3, 4, -1, -1, 7, -1, -1, -1, 9, 0, 5, 10, 0, 11}},
|
||||
{A8000, {0, 3, 4, 5, -1, 7, -1, -1, -1, -1, -1, -1, 10, -1, -1}},
|
||||
{DME1737, {0, 3, 4, 5, -1, 7, -1, -1, -1, -1, -1, -1, 10, -1, -1}},
|
||||
{SCH3112, {0, 3, 4, 5, -1, 7, -1, -1, -1, -1, -1, -1, 10, -1, -1}},
|
||||
|
|
|
|||
|
|
@ -0,0 +1,41 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2009 Michael Gold <mgold@ncf.ca>
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; either version 2 of the License, or
|
||||
## (at your option) any later version.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
|
||||
target 6513wu
|
||||
mainboard mitac/6513wu
|
||||
|
||||
# Leave 32 KB free for VGA BIOS.
|
||||
option CONFIG_ROM_SIZE = (512 - 32) * 1024
|
||||
|
||||
option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
|
||||
|
||||
romimage "normal"
|
||||
option CONFIG_USE_FALLBACK_IMAGE = 0
|
||||
option COREBOOT_EXTRA_VERSION = ".0Normal"
|
||||
payload ../payload.elf
|
||||
end
|
||||
|
||||
romimage "fallback"
|
||||
option CONFIG_USE_FALLBACK_IMAGE = 1
|
||||
option COREBOOT_EXTRA_VERSION = ".0Fallback"
|
||||
payload ../payload.elf
|
||||
end
|
||||
|
||||
buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
|
||||
Loading…
Reference in New Issue