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intel: Define `RCBA_LENGTH` in Kconfig and use it 

Change-Id: Ief81d49f04c1743b2a37633c4a35da9d6ddb0974
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50039
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2021-01-28 14:27:46 +01:00 committed by Patrick Georgi
parent ca935d1107
commit b70ff52b83
14 changed files with 17 additions and 13 deletions
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2
src/northbridge/intel/gm45/acpi/gm45.asl
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@ -13,7 +13,7 @@ Device (PDRC)
// This does not seem to work correctly yet - set values statically for // This does not seem to work correctly yet - set values statically for
// now. // now.
Name (PDRS, ResourceTemplate() { Name (PDRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, CONFIG_FIXED_RCBA_MMIO_BASE, 0x00004000) Memory32Fixed(ReadWrite, CONFIG_FIXED_RCBA_MMIO_BASE, CONFIG_RCBA_LENGTH)
Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000) Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000)
Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000)
Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000)

2
src/northbridge/intel/haswell/acpi/hostbridge.asl
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@ -174,7 +174,7 @@ Device (PDRC)
Name (_UID, 1) Name (_UID, 1)
Name (PDRS, ResourceTemplate () { Name (PDRS, ResourceTemplate () {
Memory32Fixed (ReadWrite, CONFIG_FIXED_RCBA_MMIO_BASE, 0x00004000) Memory32Fixed (ReadWrite, CONFIG_FIXED_RCBA_MMIO_BASE, CONFIG_RCBA_LENGTH)
Memory32Fixed (ReadWrite, DEFAULT_MCHBAR, 0x00008000) Memory32Fixed (ReadWrite, DEFAULT_MCHBAR, 0x00008000)
Memory32Fixed (ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed (ReadWrite, DEFAULT_DMIBAR, 0x00001000)
Memory32Fixed (ReadWrite, DEFAULT_EPBAR, 0x00001000) Memory32Fixed (ReadWrite, DEFAULT_EPBAR, 0x00001000)

2
src/northbridge/intel/i945/acpi/i945.asl
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@ -37,7 +37,7 @@ Device (PDRC)
//}) //})
Name (PDRS, ResourceTemplate() { Name (PDRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, CONFIG_FIXED_RCBA_MMIO_BASE, 0x00004000) Memory32Fixed(ReadWrite, CONFIG_FIXED_RCBA_MMIO_BASE, CONFIG_RCBA_LENGTH)
Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000) Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000)
Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000)
Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000)

2
src/northbridge/intel/ironlake/acpi/ironlake.asl
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@ -10,7 +10,7 @@ Device (PDRC)
Name (_UID, 1) Name (_UID, 1)
Name (PDRS, ResourceTemplate() { Name (PDRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, CONFIG_FIXED_RCBA_MMIO_BASE, 0x00004000) Memory32Fixed(ReadWrite, CONFIG_FIXED_RCBA_MMIO_BASE, CONFIG_RCBA_LENGTH)
Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00008000) Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00008000)
Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000)
Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000)

2
src/northbridge/intel/pineview/acpi/pineview.asl
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@ -12,7 +12,7 @@ Device (PDRC)
/* This does not seem to work correctly yet - set values statically for now. */ /* This does not seem to work correctly yet - set values statically for now. */
Name (PDRS, ResourceTemplate() { Name (PDRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, CONFIG_FIXED_RCBA_MMIO_BASE, 0x00004000) Memory32Fixed(ReadWrite, CONFIG_FIXED_RCBA_MMIO_BASE, CONFIG_RCBA_LENGTH)
Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000) Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000)
Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000)
Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000)

2
src/northbridge/intel/sandybridge/acpi/sandybridge.asl
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@ -10,7 +10,7 @@ Device (PDRC)
Name (_UID, 1) Name (_UID, 1)
Name (PDRS, ResourceTemplate() { Name (PDRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, CONFIG_FIXED_RCBA_MMIO_BASE, 0x00004000) Memory32Fixed(ReadWrite, CONFIG_FIXED_RCBA_MMIO_BASE, CONFIG_RCBA_LENGTH)
// Filled by _CRS // Filled by _CRS
Memory32Fixed(ReadWrite, 0, 0x00008000, MCHB) Memory32Fixed(ReadWrite, 0, 0x00008000, MCHB)
Memory32Fixed(ReadWrite, 0, 0x00001000, DMIB) Memory32Fixed(ReadWrite, 0, 0x00001000, DMIB)

2
src/northbridge/intel/x4x/acpi/x4x.asl
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@ -10,7 +10,7 @@ Device (PDRC)
Name (_UID, 1) Name (_UID, 1)
Name (PDRS, ResourceTemplate() { Name (PDRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, CONFIG_FIXED_RCBA_MMIO_BASE, 0x00004000) Memory32Fixed(ReadWrite, CONFIG_FIXED_RCBA_MMIO_BASE, CONFIG_RCBA_LENGTH)
Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000) Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000)
Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000)
Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000)

2
src/southbridge/intel/bd82x6x/acpi/pch.asl
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@ -181,7 +181,7 @@ Scope(\)
// ICH7 Root Complex Register Block. Memory Mapped through RCBA) // ICH7 Root Complex Register Block. Memory Mapped through RCBA)
OperationRegion(RCRB, SystemMemory, CONFIG_FIXED_RCBA_MMIO_BASE, 0x4000) OperationRegion(RCRB, SystemMemory, CONFIG_FIXED_RCBA_MMIO_BASE, CONFIG_RCBA_LENGTH)
Field(RCRB, DWordAcc, Lock, Preserve) Field(RCRB, DWordAcc, Lock, Preserve)
{ {
Offset(0x0000), // Backbone Offset(0x0000), // Backbone

4
src/southbridge/intel/common/Kconfig
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@ -108,6 +108,10 @@ config FIXED_RCBA_MMIO_BASE
hex hex
default 0xfed1c000 default 0xfed1c000
config RCBA_LENGTH
hex
default 0x4000
config FIXED_SMBUS_IO_BASE config FIXED_SMBUS_IO_BASE
hex hex
depends on SOUTHBRIDGE_INTEL_COMMON_SMBUS depends on SOUTHBRIDGE_INTEL_COMMON_SMBUS

2
src/southbridge/intel/i82801gx/acpi/ich7.asl
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@ -110,7 +110,7 @@ Scope(\)
// ICH7 Root Complex Register Block. Memory Mapped through RCBA) // ICH7 Root Complex Register Block. Memory Mapped through RCBA)
OperationRegion(RCRB, SystemMemory, CONFIG_FIXED_RCBA_MMIO_BASE, 0x4000) OperationRegion(RCRB, SystemMemory, CONFIG_FIXED_RCBA_MMIO_BASE, CONFIG_RCBA_LENGTH)
Field(RCRB, DWordAcc, Lock, Preserve) Field(RCRB, DWordAcc, Lock, Preserve)
{ {
// Backbone // Backbone

2
src/southbridge/intel/i82801ix/acpi/ich9.asl
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@ -110,7 +110,7 @@ Scope(\)
// ICH9 Root Complex Register Block. Memory Mapped through RCBA) // ICH9 Root Complex Register Block. Memory Mapped through RCBA)
OperationRegion(RCRB, SystemMemory, CONFIG_FIXED_RCBA_MMIO_BASE, 0x4000) OperationRegion(RCRB, SystemMemory, CONFIG_FIXED_RCBA_MMIO_BASE, CONFIG_RCBA_LENGTH)
Field(RCRB, DWordAcc, Lock, Preserve) Field(RCRB, DWordAcc, Lock, Preserve)
{ {
Offset(0x0000), // Backbone Offset(0x0000), // Backbone

2
src/southbridge/intel/i82801jx/acpi/ich10.asl
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@ -112,7 +112,7 @@ Scope(\)
// ICH10 Root Complex Register Block. Memory Mapped through RCBA) // ICH10 Root Complex Register Block. Memory Mapped through RCBA)
OperationRegion(RCRB, SystemMemory, CONFIG_FIXED_RCBA_MMIO_BASE, 0x4000) OperationRegion(RCRB, SystemMemory, CONFIG_FIXED_RCBA_MMIO_BASE, CONFIG_RCBA_LENGTH)
Field(RCRB, DWordAcc, Lock, Preserve) Field(RCRB, DWordAcc, Lock, Preserve)
{ {
Offset(0x0000), // Backbone Offset(0x0000), // Backbone

2
src/southbridge/intel/lynxpoint/acpi/pch.asl
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@ -19,7 +19,7 @@ Scope (\)
} }
// Root Complex Register Block // Root Complex Register Block
OperationRegion (RCRB, SystemMemory, CONFIG_FIXED_RCBA_MMIO_BASE, 0x4000) OperationRegion (RCRB, SystemMemory, CONFIG_FIXED_RCBA_MMIO_BASE, CONFIG_RCBA_LENGTH)
Field (RCRB, DWordAcc, Lock, Preserve) Field (RCRB, DWordAcc, Lock, Preserve)
{ {
Offset (0x3404), // High Performance Timer Configuration Offset (0x3404), // High Performance Timer Configuration

2
src/southbridge/intel/lynxpoint/lpc.c
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@ -560,7 +560,7 @@ static void pch_lpc_add_mmio_resources(struct device *dev)
if (CONFIG_FIXED_RCBA_MMIO_BASE < default_decode_base) { if (CONFIG_FIXED_RCBA_MMIO_BASE < default_decode_base) {
res = new_resource(dev, RCBA); res = new_resource(dev, RCBA);
res->base = (resource_t)CONFIG_FIXED_RCBA_MMIO_BASE; res->base = (resource_t)CONFIG_FIXED_RCBA_MMIO_BASE;
res->size = 16 * 1024; res->size = CONFIG_RCBA_LENGTH;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |
IORESOURCE_FIXED | IORESOURCE_RESERVE; IORESOURCE_FIXED | IORESOURCE_RESERVE;
} }