From b717e48352fe5466a92431f1597b85f902d75673 Mon Sep 17 00:00:00 2001 From: Greg Watson Date: Thu, 22 Apr 2004 22:31:49 +0000 Subject: [PATCH] start of epia-m port git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1524 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/include/device/pci_ids.h | 1 + src/mainboard/via/epia-m/auto.c | 9 ++- src/mainboard/via/epia-m/chip.h | 4 +- src/mainboard/via/epia-m/cmos.layout | 74 +++++++++++++++++++ src/southbridge/via/vt8235/vt8235.c | 14 ++-- .../via/vt8235/vt8235_early_serial.c | 53 +++++++------ .../via/vt8235/vt8235_early_smbus.c | 35 +++++---- 7 files changed, 140 insertions(+), 50 deletions(-) create mode 100644 src/mainboard/via/epia-m/cmos.layout diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 23fc13c58f..586083a966 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -1011,6 +1011,7 @@ #define PCI_DEVICE_ID_VIA_86C100A 0x6100 #define PCI_DEVICE_ID_VIA_8231 0x8231 #define PCI_DEVICE_ID_VIA_8231_4 0x8235 +#define PCI_DEVICE_ID_VIA_8235 0x3177 #define PCI_DEVICE_ID_VIA_8365_1 0x8305 #define PCI_DEVICE_ID_VIA_8371_1 0x8391 #define PCI_DEVICE_ID_VIA_8501_1 0x8501 diff --git a/src/mainboard/via/epia-m/auto.c b/src/mainboard/via/epia-m/auto.c index 20e85e4645..88523ed9e9 100644 --- a/src/mainboard/via/epia-m/auto.c +++ b/src/mainboard/via/epia-m/auto.c @@ -2,6 +2,7 @@ #include #include +#include #include #include #include @@ -26,10 +27,10 @@ void udelay(int usecs) #include "cpu/p6/boot_cpu.c" #include "debug.c" -#include "southbridge/via/vt8231/vt8235_early_smbus.c" +#include "southbridge/via/vt8235/vt8235_early_smbus.c" -#include "southbridge/via/vt8231/vt8235_early_serial.c" +#include "southbridge/via/vt8235/vt8235_early_serial.c" static void memreset_setup(void) { } @@ -58,7 +59,7 @@ static void enable_mainboard_devices(void) device_t dev; /* dev 0 for southbridge */ - dev = pci_locate_device(PCI_ID(0x1106,0x8235), 0); + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235), 0); if (dev == PCI_DEV_INVALID) { die("Southbridge not found!!!\n"); @@ -99,13 +100,13 @@ static void main(void) /* init_timer();*/ outb(5, 0x80); + enable_smbus(); enable_vt8235_serial(); uart_init(); console_init(); enable_mainboard_devices(); - enable_smbus(); enable_shadow_ram(); /* memreset_setup(); diff --git a/src/mainboard/via/epia-m/chip.h b/src/mainboard/via/epia-m/chip.h index 94b632b5a8..922b4c44ff 100644 --- a/src/mainboard/via/epia-m/chip.h +++ b/src/mainboard/via/epia-m/chip.h @@ -1,5 +1,5 @@ -struct chip_control mainboard_via_epia_control; +struct chip_control mainboard_via_epia_m_control; -struct mainboard_via_epia_config { +struct mainboard_via_epia_m_config { int nothing; }; diff --git a/src/mainboard/via/epia-m/cmos.layout b/src/mainboard/via/epia-m/cmos.layout new file mode 100644 index 0000000000..5ba4c032c1 --- /dev/null +++ b/src/mainboard/via/epia-m/cmos.layout @@ -0,0 +1,74 @@ +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +1008 16 h 0 check_sum + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM + +checksums + +checksum 392 1007 1008 + + diff --git a/src/southbridge/via/vt8235/vt8235.c b/src/southbridge/via/vt8235/vt8235.c index 8d5292fad2..ca5ab32ac3 100644 --- a/src/southbridge/via/vt8235/vt8235.c +++ b/src/southbridge/via/vt8235/vt8235.c @@ -229,7 +229,7 @@ static void vt8235_init(struct southbridge_via_vt8235_config *conf) /* IDE controller */ dev1 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, 0); /* Power management controller */ - devpwr = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_4, 0); + //devpwr = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_4, 0); // enable the internal I/O decode enables = pci_read_config8(dev0, 0x6C); @@ -315,22 +315,22 @@ static void vt8235_init(struct southbridge_via_vt8235_config *conf) // Power management setup // // Set ACPI base address to IO 0x4000 - pci_write_config32(devpwr, 0x48, 0x4001); + //pci_write_config32(devpwr, 0x48, 0x4001); // Enable ACPI access (and setup like award) - pci_write_config8(devpwr, 0x41, 0x84); + //pci_write_config8(devpwr, 0x41, 0x84); // Set hardware monitor base address to IO 0x6000 - pci_write_config32(devpwr, 0x70, 0x6001); + //pci_write_config32(devpwr, 0x70, 0x6001); // Enable hardware monitor (and setup like award) - pci_write_config8(devpwr, 0x74, 0x01); + //pci_write_config8(devpwr, 0x74, 0x01); // set IO base address to 0x5000 - pci_write_config32(devpwr, 0x90, 0x5001); + //pci_write_config32(devpwr, 0x90, 0x5001); // Enable SMBus - pci_write_config8(devpwr, 0xd2, 0x01); + //pci_write_config8(devpwr, 0xd2, 0x01); // // IDE setup diff --git a/src/southbridge/via/vt8235/vt8235_early_serial.c b/src/southbridge/via/vt8235/vt8235_early_serial.c index 4e59bbf3ec..3191057811 100644 --- a/src/southbridge/via/vt8235/vt8235_early_serial.c +++ b/src/southbridge/via/vt8235/vt8235_early_serial.c @@ -8,12 +8,19 @@ #define SIO_BASE 0x3f0 #define SIO_DATA SIO_BASE+1 -static void vt8235_writesuper(uint8_t reg, uint8_t val) +static void vt8235_writepnpaddr(uint8_t val) { - outb(reg, SIO_BASE); - outb(val, SIO_DATA); + outb(val, 0x2e); + outb(val, 0xeb); } +static void vt8235_writepnpdata(uint8_t val) +{ + outb(val, 0x2f); + outb(val, 0xeb); +} + + static void vt8235_writesiobyte(uint16_t reg, uint8_t val) { outb(val, reg); @@ -34,30 +41,28 @@ static void enable_vt8235_serial(void) unsigned long x; uint8_t c; device_t dev; - outb(6, 0x80); - dev = pci_locate_device(PCI_ID(0x1106,0x8235), 0); - - if (dev == PCI_DEV_INVALID) { - outb(7, 0x80); - die("Serial controller not found\r\n"); - } - - /* first, you have to enable the superio and superio config. - put a 6 reg 80 - */ - c = pci_read_config8(dev, 0x50); - c |= 6; - pci_write_config8(dev, 0x50, c); - outb(2, 0x80); + // turn on pnp + vt8235_writepnpaddr(0x87); + vt8235_writepnpaddr(0x87); // now go ahead and set up com1. // set address - vt8235_writesuper(0xf4, 0xfe); + vt8235_writepnpaddr(0x7); + vt8235_writepnpdata(0x2); // enable serial out - vt8235_writesuper(0xf2, 7); - // That's it for the sio stuff. - // movl $SUPERIOCONFIG, %eax - // movb $9, %dl - // PCI_WRITE_CONFIG_BYTE + vt8235_writepnpaddr(0x30); + vt8235_writepnpdata(0x1); + // serial port 1 base address (FEh) + vt8235_writepnpaddr(0x60); + vt8235_writepnpdata(0xfe); + // serial port 1 IRQ (04h) + vt8235_writepnpaddr(0x70); + vt8235_writepnpdata(0x4); + // serial port 1 control + vt8235_writepnpaddr(0xf0); + vt8235_writepnpdata(0x2); + // turn of pnp + vt8235_writepnpaddr(0xaa); + // set up reg to set baud rate. vt8235_writesiobyte(0x3fb, 0x80); // Set 115 kb diff --git a/src/southbridge/via/vt8235/vt8235_early_smbus.c b/src/southbridge/via/vt8235/vt8235_early_smbus.c index 9d03dacd44..79b73df01e 100644 --- a/src/southbridge/via/vt8235/vt8235_early_smbus.c +++ b/src/southbridge/via/vt8235/vt8235_early_smbus.c @@ -1,4 +1,4 @@ -#define SMBUS_IO_BASE 0x5000 +#define SMBUS_IO_BASE 0xf00 #define SMBHSTSTAT 0x0 #define SMBSLVSTAT 0x1 @@ -22,12 +22,15 @@ #define SMBUS_TIMEOUT (100*1000*10) +#define I2C_TRANS_CMD 0x40 +#define CLOCK_SLAVE_ADDRESS 0x69 + static void enable_smbus(void) { device_t dev; unsigned char c; /* Power management controller */ - dev = pci_locate_device(PCI_ID(0x1106,0x8235), 0); + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235), 0); if (dev == PCI_DEV_INVALID) { die("SMBUS controller not found\r\n"); @@ -37,20 +40,26 @@ static void enable_smbus(void) pci_write_config32(dev, 0x90, SMBUS_IO_BASE|1); // Enable SMBus - c = pci_read_config8(dev, 0xd2); - c |= 5; - pci_write_config8(dev, 0xd2, c); + pci_write_config8(dev, 0xd2, (0x4 << 1)|1); /* make it work for I/O ... */ - dev = pci_locate_device(PCI_ID(0x1106,0x8235), 0); - c = pci_read_config8(dev, 4); - c |= 1; - pci_write_config8(dev, 4, c); - print_debug_hex8(c); - print_debug(" is the comm register\r\n"); - - print_debug("SMBus controller enabled\r\n"); + pci_write_config8(dev, 4, 1); + +/* The VT1211 serial port needs 48 mhz clock, on power up it is getting + only 24 mhz, there is some mysterious device on the smbus that can + fix this...this code below does it. */ + outb(0xff, SMBUS_IO_BASE+SMBHSTSTAT); + outb(0x7f, SMBUS_IO_BASE+SMBHSTDAT0); + outb(0x83, SMBUS_IO_BASE+SMBHSTCMD); + outb(CLOCK_SLAVE_ADDRESS<<1, SMBUS_IO_BASE+SMBXMITADD); + outb(8 | I2C_TRANS_CMD, SMBUS_IO_BASE+SMBHSTCTL); + + for (;;) { + c = inb(SMBUS_IO_BASE+SMBHSTSTAT); + if (c & 1 == 0) + break; + } }