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Broadwell: Select PCIE_L1_SUB_STATE and apply Broadwell settings. 

Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
BUG=chrome-os-partner:31424
TEST=Build an image and confirm the settings are correctly applied
     to registers for PCIe L1 Sub-State feature enabling.

Original-Commit-Id: b94c8c715febe3a04bfdf52f7b69d73ece0f6faf
Original-Signed-off-by: Kenji Chen <kenji.chen@intel.com>
Original-Change-Id: I07ce6eea648b1b37d606f5529edad184e3de70ac
Original-Reviewed-on: https://chromium-review.googlesource.com/222599
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>

Change-Id: I07336599797c09bf23e5b15059d6ad812fdc7c61
Reviewed-on: http://review.coreboot.org/9223
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
Kenji Chen 2014-10-10 03:08:15 +08:00 committed by Stefan Reinauer
parent 1d84ef57c2
commit b71d9b8a0f
2 changed files with 8 additions and 0 deletions
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1
src/soc/intel/broadwell/Kconfig
View File

@ -36,6 +36,7 @@ config CPU_SPECIFIC_OPTIONS
select PCIEXP_ASPM
select PCIEXP_COMMON_CLOCK
select PCIEXP_CLK_PM
select PCIEXP_L1_SUB_STATE
select SMM_MODULES
select SMM_TSEG
select SMP

7
src/soc/intel/broadwell/pcie.c
View File

@ -651,8 +651,15 @@ static void pcie_set_subsystem(device_t dev, unsigned vendor, unsigned device)
pci_write_config32(dev, 0x94, (device << 16) | vendor);
}
static void pcie_set_L1_ss_max_latency(device_t dev, unsigned int off)
{
/* Set max snoop and non-snoop latency for Broadwell */
pci_mmio_write_config32(dev, off, 0x10031003);
}
static struct pci_operations pcie_ops = {
.set_subsystem = pcie_set_subsystem,
.set_L1_ss_latency = pcie_set_L1_ss_max_latency,
};
static struct device_operations device_ops = {