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northbridge/intel/fsp_rangeley: Correct MMIO size setting 

The Rangeley chipset has the MMIO PCI config space feature
enabled at 0xe0000000-0xefffffff. This is a 256MB space
which covers all of config space. The ACPI table for
this space only defines it as being 64MB. This change
fixes that setting.

Change-Id: I8205a9b89ea6633ac6c4b0d5a282cd2745595b2e
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/10047
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Tested-by: build bot (Jenkins)
This commit is contained in:
Dave Frodin 2015-05-01 09:17:43 -06:00
parent 2eaa0d49e1
commit b738913ce0
1 changed files with 1 additions and 1 deletions
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src/northbridge/intel/fsp_rangeley/acpi/rangeley.asl
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@ -30,7 +30,7 @@ Device (PDRC)
Name (_UID, 1)
Name (PDRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, DEFAULT_ECBASE, 0x04000000)
Memory32Fixed(ReadWrite, DEFAULT_ECBASE, 0x10000000)
})
// Current Resource Settings