GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mb/google/brask/variants/moli: change clk_src and clk_req for LAN_I225V 

change clk_src and clk_req to 4 for LAN_I225V based on
ADL_Moli_SC_MB_20220601.pdf.

BUG=b:235768639
TEST=emerge-brask coreboot and check LAN_I225V can connect.

Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: I323726df84d07703402da9da44b1882a0cdc1e33
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65105
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Raihow Shi 2022-06-13 16:49:52 +08:00 committed by Felix Held
parent d79bb899c1
commit b73cb4b1d2
1 changed files with 3 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/mainboard/google/brya/variants/moli/overridetree.cb
View File

@ -83,10 +83,10 @@ chip soc/intel/alderlake
end end
end # Audio Nau8825 end # Audio Nau8825
device ref pcie_rp6 on device ref pcie_rp6 on
# Enable PCIe-to-i225 bridge PCIe 6 using clk 5 # Enable PCIe-to-i225 bridge PCIe 6 using clk 4
register "pch_pcie_rp[PCH_RP(6)]" = "{ register "pch_pcie_rp[PCH_RP(6)]" = "{
.clk_src = 5, .clk_src = 4,
.clk_req = 5, .clk_req = 4,
.flags = PCIE_RP_LTR | PCIE_RP_AER, .flags = PCIE_RP_LTR | PCIE_RP_AER,
.pcie_rp_aspm = ASPM_DISABLE, .pcie_rp_aspm = ASPM_DISABLE,
}" }"