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vc/amd/agesa/[...]/Proc/Mem: Delete unused function 

The generic MemNProgramNbPstateDependentRegistersUnb function is unused,
and generates a Coverity warning of an unused switch case. Only family
specific versions of this function are called elsewhere. Delete unused
function.

Change-Id: I2afc83861f4b3a13bfc1eef4920cd3023e608e94
Signed-off-by: Joe Moore <awokd@danwin1210.me>
Found-by: Coverity CID 1241810
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38493
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Joe Moore 2020-01-21 02:30:04 -07:00 committed by Patrick Georgi
parent b5b5490bbd
commit b753006f38
4 changed files with 0 additions and 115 deletions
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56
src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mndct.c
View File

@ -1933,62 +1933,6 @@ MemNChangeFrequencyUnb (
} }
} }
/* -----------------------------------------------------------------------------*/
/**
*
* This function calculates and programs NB P-state dependent registers
*
* @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
*
*/
VOID
MemNProgramNbPstateDependentRegistersUnb (
IN OUT MEM_NB_BLOCK *NBPtr
)
{
UINT8 RdPtrInit;
UINT8 Dct;
RdPtrInit = (NBPtr->DCTPtr->Timings.Speed <= DDR1600_FREQUENCY) ? 6 : 5;
MemNBrdcstSetNb (NBPtr, BFRdPtrInit, RdPtrInit);
IDS_HDT_CONSOLE (MEM_FLOW, "\t\tRdPtr: %d\n", RdPtrInit);
switch (RdPtrInit) {
case 4:
if (MemNGetBitFieldNb (NBPtr, BFNbPsSel) == 0) {
MemNBrdcstSetNb (NBPtr, BFDataTxFifoWrDly, 2);
} else {
MemNBrdcstSetNb (NBPtr, BFDataTxFifoWrDly, 1);
}
break;
case 5:
MemNBrdcstSetNb (NBPtr, BFDataTxFifoWrDly, 1);
break;
case 6:
MemNBrdcstSetNb (NBPtr, BFDataTxFifoWrDly, 0);
break;
default:
ASSERT (FALSE);
}
for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
MemNSwitchDCTNb (NBPtr, Dct);
if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
// Set ProcOdtAdv
if (NBPtr->DCTPtr->Timings.Speed <= DDR1333_FREQUENCY) {
MemNSetBitFieldNb (NBPtr, BFProcOdtAdv, 0);
} else {
MemNSetBitFieldNb (NBPtr, BFProcOdtAdv, 0x4000);
}
}
}
NBPtr->FamilySpecificHook[OverrideDataTxFifoWrDly] (NBPtr, NBPtr);
IDS_OPTION_HOOK (IDS_NBPS_REG_OVERRIDE, NBPtr, &NBPtr->MemPtr->StdHeader);
}
/* -----------------------------------------------------------------------------*/ /* -----------------------------------------------------------------------------*/
CONST UINT8 PllDivTab[] = {0, 0, 0, 2, 3, 3, 2, 3}; CONST UINT8 PllDivTab[] = {0, 0, 0, 2, 3, 3, 2, 3};
CONST UINT8 PllMultTab[] = {0, 0, 0, 16, 32, 40, 32, 56}; CONST UINT8 PllMultTab[] = {0, 0, 0, 16, 32, 40, 32, 56};

5
src/vendorcode/amd/agesa/f14/Proc/Mem/mn.h
View File

@ -1185,11 +1185,6 @@ MemNChangeFrequencyUnb (
IN OUT MEM_NB_BLOCK *NBPtr IN OUT MEM_NB_BLOCK *NBPtr
); );
VOID
MemNProgramNbPstateDependentRegistersUnb (
IN OUT MEM_NB_BLOCK *NBPtr
);
VOID VOID
MemNProgramNbPstateDependentRegistersClientNb ( MemNProgramNbPstateDependentRegistersClientNb (
IN OUT MEM_NB_BLOCK *NBPtr IN OUT MEM_NB_BLOCK *NBPtr

49
src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mndct.c
View File

@ -2310,55 +2310,6 @@ MemNChangeFrequencyUnb (
MemFInitTableDrive (NBPtr, MTAfterFreqChg); MemFInitTableDrive (NBPtr, MTAfterFreqChg);
} }
/* -----------------------------------------------------------------------------*/
/**
*
* This function calculates and programs NB P-state dependent registers
*
* @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
*
*/
VOID
MemNProgramNbPstateDependentRegistersUnb (
IN OUT MEM_NB_BLOCK *NBPtr
)
{
UINT8 RdPtrInit;
RdPtrInit = (NBPtr->DCTPtr->Timings.Speed <= DDR1600_FREQUENCY) ? 6 : 4;
MemNBrdcstSetNb (NBPtr, BFRdPtrInit, RdPtrInit);
IDS_HDT_CONSOLE (MEM_FLOW, "\t\tRdPtr: %d\n", RdPtrInit);
MemFInitTableDrive (NBPtr, MTAfterNbPstateChange);
IDS_HDT_CONSOLE_DEBUG_CODE (
RdPtrInit = (UINT8) MemNGetBitFieldNb (NBPtr, BFRdPtrInit);
);
switch (RdPtrInit) {
case 4:
if (MemNGetBitFieldNb (NBPtr, BFNbPsSel) == 0) {
MemNBrdcstSetNb (NBPtr, BFDataTxFifoWrDly, 2);
} else {
MemNBrdcstSetNb (NBPtr, BFDataTxFifoWrDly, 1);
}
break;
case 5:
MemNBrdcstSetNb (NBPtr, BFDataTxFifoWrDly, 1);
break;
case 6:
MemNBrdcstSetNb (NBPtr, BFDataTxFifoWrDly, 0);
break;
default:
ASSERT (FALSE);
}
NBPtr->FamilySpecificHook[OverrideDataTxFifoWrDly] (NBPtr, NBPtr);
IDS_OPTION_HOOK (IDS_NBPS_REG_OVERRIDE, NBPtr, &NBPtr->MemPtr->StdHeader);
}
/* -----------------------------------------------------------------------------*/ /* -----------------------------------------------------------------------------*/
CONST UINT8 PllDivTab[] = {0, 0, 0, 2, 3, 3, 2, 3}; CONST UINT8 PllDivTab[] = {0, 0, 0, 2, 3, 3, 2, 3};
CONST UINT8 PllMultTab[] = {0, 0, 0, 16, 32, 40, 32, 56}; CONST UINT8 PllMultTab[] = {0, 0, 0, 16, 32, 40, 32, 56};

5
src/vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h
View File

@ -1289,11 +1289,6 @@ MemNChangeFrequencyUnb (
IN OUT MEM_NB_BLOCK *NBPtr IN OUT MEM_NB_BLOCK *NBPtr
); );
VOID
MemNProgramNbPstateDependentRegistersUnb (
IN OUT MEM_NB_BLOCK *NBPtr
);
VOID VOID
MemNProgramNbPstateDependentRegistersClientNb ( MemNProgramNbPstateDependentRegistersClientNb (
IN OUT MEM_NB_BLOCK *NBPtr IN OUT MEM_NB_BLOCK *NBPtr