diff --git a/src/soc/amd/picasso/acpi/globalnvs.asl b/src/soc/amd/picasso/acpi/globalnvs.asl
index 6e63b8da5e..6790a5f4a6 100644
--- a/src/soc/amd/picasso/acpi/globalnvs.asl
+++ b/src/soc/amd/picasso/acpi/globalnvs.asl
@@ -25,19 +25,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 	TMPS,	8,	// 0x17 - Temperature Sensor ID
 	TCRT,	8,	// 0x18 - Critical Threshold
 	TPSV,	8,	// 0x19 - Passive Threshold
-	Offset (0x20),  // 0x20 - AOAC Device Enables
-	, 7,
-	IC2E,	1,	//        I2C2, 7
-	IC3E,	1,	//        I2C3, 8
-	IC4E,	1,	//        I2C4, 9
-	, 1,
-	UT0E,	1,	//        UART0, 11
-	UT1E,	1,	//        UART1, 12
-	, 3,
-	UT2E,	1,	//        UART2, 16
-	, 9,
-	UT23,	1,	//        UART3, 26
-	ESPI,	1,	//        ESPI, 27
 	/* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */
 	Offset (0x100),
 	#include <vendorcode/google/chromeos/acpi/gnvs.asl>
diff --git a/src/soc/amd/picasso/include/soc/nvs.h b/src/soc/amd/picasso/include/soc/nvs.h
index b6708c8502..2abcdd31f7 100644
--- a/src/soc/amd/picasso/include/soc/nvs.h
+++ b/src/soc/amd/picasso/include/soc/nvs.h
@@ -25,9 +25,7 @@ struct __packed global_nvs {
 	uint8_t		tmps; /* 0x17 - Temperature Sensor ID */
 	uint8_t		tcrt; /* 0x18 - Critical Threshold */
 	uint8_t		tpsv; /* 0x19 - Passive Threshold */
-	uint8_t		pad1[6];
-	aoac_devs_t	aoac; /* 0x20 - AOAC device enables */
-	uint8_t		unused[220];
+	uint8_t		unused[230];
 
 	/* ChromeOS specific (0x100 - 0xfff) */
 	chromeos_acpi_t chromeos;
diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c
index 54d7640098..0b45c10222 100644
--- a/src/soc/amd/picasso/southbridge.c
+++ b/src/soc/amd/picasso/southbridge.c
@@ -347,22 +347,6 @@ void southbridge_init(void *chip_info)
 	al2ahb_clock_gate();
 }
 
-static void set_sb_final_nvs(void)
-{
-	struct global_nvs *gnvs = acpi_get_gnvs();
-	if (gnvs == NULL)
-		return;
-
-	gnvs->aoac.ic2e = is_aoac_device_enabled(FCH_AOAC_DEV_I2C2);
-	gnvs->aoac.ic3e = is_aoac_device_enabled(FCH_AOAC_DEV_I2C3);
-	gnvs->aoac.ic4e = is_aoac_device_enabled(FCH_AOAC_DEV_I2C4);
-	gnvs->aoac.ut0e = is_aoac_device_enabled(FCH_AOAC_DEV_UART0);
-	gnvs->aoac.ut1e = is_aoac_device_enabled(FCH_AOAC_DEV_UART1);
-	gnvs->aoac.ut2e = is_aoac_device_enabled(FCH_AOAC_DEV_UART2);
-	gnvs->aoac.ut3e = is_aoac_device_enabled(FCH_AOAC_DEV_UART3);
-	gnvs->aoac.espi = 1;
-}
-
 void southbridge_final(void *chip_info)
 {
 	uint8_t restored_power = PM_S5_AT_POWER_RECOVERY;
@@ -370,8 +354,6 @@ void southbridge_final(void *chip_info)
 	if (CONFIG(MAINBOARD_POWER_RESTORE))
 		restored_power = PM_RESTORE_S0_IF_PREV_S0;
 	pm_write8(PM_RTC_SHADOW, restored_power);
-
-	set_sb_final_nvs();
 }
 
 /*